Investigation of Dielectric

Modulated DG-MOSFET with

different configuration for
biosensor applications

GUIDED BY:-
Dr. Sanjit Kumar Swain
GROUP MEMBERS:-
1 1.Anisha Aditi-1501209329
2.Asmit Amlan Sahoo-1501209335
Department Of Electronics and Telecommunication Engineeri
3.L. Sujana-1501209368
Silicon Institute Of Technology
4..Sonali Panda-1501209420 Bhubaneswar-751024
5. Soumya Ranjan Padhy-1501209423
6.Rama Sai Sandeep-1501209458
2 CONTENTS
 INTRODUCTION

 WHY DO WE NEED SCALING

 SHORT CHANNEL EFFECTS

 DOUBLE-GATE MOSFET --- STRUCTURE, ADVANTAGES & DISADVANTAGES

 Gate Stack Double Gate MOSFET -AS AN ALTERNATIVE DEVICE

 EFFECTS OF BIOMOLECULES

 APPLICATION AS BIOSENSOR

 LITRETURE SURVEY

 RESULTS AND ANALYSIS

 FUTURE WORK

 CONCLUSION

 REFERNCES
 INTRODUCTION
3

 Downscaling of device dimensions along with the rapid evolution in the

CMOS technology and innovation in the device design led to an denser
and faster IC’s .
 Increased performance levels and reduced physical size .
 However the current trend of downscaling of classical bulk MOSFET
has adverse effects:-
• Short Channel Effects
• Current Drivability
 These effects present a key challenge of further downscaling of the
devices while maintaining a high device performance
4 WHY DO WE NEED SCALING?
 To have both our electronic devices and components:-
• Faster
• Smaller
• Cheaper

The continuous effort to shrink the channel length has been beneficial to both
Analog and Digital ICs such as:-

• Augmenting the Cut-Off Frequency of the RF circuit

• Enhancing the switching speed

• Increasing the packing density

5 SCALING LIMITS OF BULK
MOSFETS
 Limit for supply voltage (<0.6V)

 Limit for further scaling of tox (<2nm)

 Minimum channel length Lg=50nm

 Discrete dopant fluctuations

 Short-channels effects (SCE)

 CHALLENGES OF SCALING

6
Physical •Increment of tunnelling and leakage currents as the devices are
becoming smaller, impacting the performance and functionality
challenges: of CMOS devices.

Material •The inability of the dielectric and wiring materials to provide

reliable insulation and conduction, respectively with continued
challenges scaling.

Power-thermal The ever increasing number of transistors integrated per unit-

●

area demands larger power consumption and higher thermal

challenges dissipation.

Technological •The incompetent lithography techniques don’t provide the

resolution below the wavelength of the light to manufacture to
challenges CMOS devices

Economical The rise in cost of production, fabrication and testing that may
●

reach a point where it will be not feasible from economic point

challenges of view.
7
SHORT CHANNEL EFFECTS

 A MOSFET device is said to be short

when the channel length is the same
order of magnitude as the depletion-
layer widths of the source and drain
junction.

 The short-channel effects are attributed

to two physical phenomena:

• The limitation imposed on electron

drift characteristics in the channel.

• The modification of the threshold

voltage due to the shortening
channel length.
 Contd..
8

DIBL IMPACT IONIZATION HOT ELECTRONS

• In small-geometry • Especially in NMOS, due to • The high energy electrons
MOSFETs, the potential the high velocity of can enter the oxide, where
barrier is controlled by electrons in presence of they can be trapped,
both the Vgs gs
and the Vds
ds
. If high longitudinal fields giving rise to oxide
the Vds is increased, the generate electron-hole charging that can
ds
potential barrier in the pairs by impact ionization, accumulate with time and
channel decreases, leading that is, by impacting on degrade the device
to drain-induced barrier silicon atoms and ionizing performance by increasing
lowering (DIBL). them. Vth
th
and affect adversely
the gate’s control on the
drain current.
9
Contd..

THRESHOLD VOLTAGE SURFACE VELOCITY

ROLL-OFF SCATTERING SATURATION
• The source and drain • As the channel length • It which reduces the
contacts will share the becomes smaller due to transconductance in the
control of the depletion the lateral extension of saturation mode. Due to
charges. The shared the depletion layer into this at high EY, the
charges will become a
the channel region, the ELL electron drift velocity Vdd in
relatively large fraction of
increases, and the surface the channel remains
total depletion charge,
mobility becomes field- constant with the electric
which gives rise to a shift
dependent. The carrier field intensity.
in Vth
th
when the gate transport in a MOSFET is
length is decreased. confined within the narrow
inversion layer.
10
Contd..
SYMMETRIC DG- ASYMMETRIC DG-
MOSFET MOSFET
DOUBLE-
• A DG-MOSFET is said • An Asymmetric DG-
GATE
to be Symmetric MOSFET either has MOSFET
when both gates synchronized but
have the same ΦGC different input
and a single input voltages to both of
voltage is applied to the identical gates,
both gates. or has the same SYMMETRIC ASYMMETRIC
input voltage to two DG-MOSFET DG-MOSFET
gates but gates
having different ΦGC .
11 ADVANTAGES OF DG- MOSFET
 Short channel effect control

• Better scalability
• Lower sub threshold current
 Higher On Current
 Near-Ideal Sub threshold slope
 Lower Gate Leakage
 Elimination of VTH variation due to
random dopant fluctuation
 DG devices are very promising for
circuit design in sub-50nm technology
12 DISADVANTAGES DG-MOSFET

 Performance degradation associated to short channel effect (e.g. DIBL)

 Performance degradation due to Hot carrier effects.

 With downscaling thin SiO2 Dielectrics lead to large gate leakage current

 Performance influenced by Inherent parasitic Bipolar effects.

13 Gate Stack DG-FET (GS DG-FET)-
An Alternative
 The doping concentration in the
channel is kept high in a region
of length L1 near the source and
low in a region of length L2 near
the drain such that the total L2

channel length, L, is given as: L

= L1+L2.
 A GC device can basically be
perceived as two sub-devices
connected in series each having
its own threshold voltage, Vth
and channel length.
14 Contd..
 In order to obtain a compact model, individual Id1 and Id2 are obtained in
the high and low-doped regions using the charge density in each part
and finally an expression for drain current in linear region is obtained
that takes into account the doping and the length of the high and low-
doped regions.

 The use of high-k dielectrics as alternative gate insulator materials to

prevent direct tunnelling leakage current.
15 SIMULATION SETUP

Bias: For Analog Analysis , Vgs=1 V For RF Analysis , Vgs=1

, Vds=1 V . V , Vds=0.5 V .
16 Literature Survey

 1
17 PROPOSED WORK
 To check for the novelty and reliability of the proposed GCGS-DG MOSFET device, we
studied the device under various variations such as;

1. Effect of spacer layer by using different high-K material

2. Variation in metal work function of the gate region

3. Comparison of the performance with respect to different gate engineering techniques

4. Comparison of performance with DG-MOSFET without considering gate engineering

techniques
 Different High-K Oxide Materials considered here are;
 ϵ=11.5 is Al2O3
 ϵ=22 is HfO2
 ϵ=8 is Si3N4
 ϵ=3.9 is SiO2
18
STUDY AND EFFECT OF SPACER
LAYER
 The DG-MOSFET shown uses
various high-k materials as
Spacers. The materials used
are:-
 ϵ=11.5 is Al2O3
 ϵ=22 is HfO2
 ϵ=8 is Si3N4
 ϵ=3.9 is SiO2
 Use of Spacer layers help in
decreasing the effect of
DIBL, impact ionization
along with other SCE effects
 Bipolar parasitic effect is
also reduced.
19 RESULTS AND ANALYSIS
 We have used various types of
materials as spacer in the GCGS
DG- MOSFET as mentioned above
and the following parameters
were analysed using simulation:-
1. Vgs vs Id ( Gate-Source Voltage vs
Drain Current)
20 Contd..
2.Transconductance vs Gate
Voltage ( gm vs Vgs)
21 Contd..
3.Total Gate to Gate
Capacitance vs Gate
Voltage (Cgg vs Vgs )
22 Future Work

 The above analysis can also be used to find various other

parameters of the proposed design such as :-
• Transconductance Generation factor
• Cut-off frequency
• RF Parameters
 Gate engineering can also be done on it by taking two different
kinds of metal and parameters such as analog parameters and
RF parameters can be found out; thereby performance analysis
can be done.
23 Conclusion

 It is concluded that by using various spacer layers on can improve the

performance of the device as there is an improvement in current
generation specially with those having higher permittivity.
 The device is more effective in lowering DIBL and other SCE effects.
Hence is more compatible with the current trend of scaling.
 Further work can be done based upon Gate engineering techniques.
24 REFERENCES
1. Kalyan Koley, Arka Dutta et al, “Analysis of High-κ Spacer Asymmetric Underlap DG-
MOSFET for SOC Application” IEEE,vol. 62, pp 1733-1738,2015.
2. S.K.Swain et al., “Effect of Channel Thickness and Doping Concentration on Sub-
Threshold Performance of Graded Channel and Gate Stack DG MOSFETs” JOLPE, vol.11, pp
366-372 , 2015.
3. D. J. Frank et al, “Device scaling limits of Si MOSFETs and their application” Proc. IEEE ,
vol.89, pp 259-288, 2001 .
4. F. Balestra, S. Cristoloveanu, M. Benachir, et al, “Double gate silicon-on-insulator with volume
inversion…” IEEE Electron Device Letters ,Vol.9,pp. 410-412 ,1987.
5. K. P. Pradhan, S. K.Mohapatra.et al, “Impact of high-K gate dielectric on analog and RF
perfomance of nanoscale DG- MOSFET…”Microelectronics journal,vol.45 pp 144-151 ,2014
25

ANY QUESTIONS ?