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Detecting and Correccting Multiple Bit Upsets in Static

The document proposes a new method to detect and correct multiple bit upsets in static random access memories using matrix codes. The existing Hamming code method has limitations as it requires more redundant bits and can only correct single or double errors. The proposed method uses a low-cost matrix code for error detection that can detect and locate multiple errors with lower area and delay overhead compared to existing complex error correction codes. Simulation results show the proposed scheme improves reliability against large multiple bit upsets in memory.

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19 views

Detecting and Correccting Multiple Bit Upsets in Static

The document proposes a new method to detect and correct multiple bit upsets in static random access memories using matrix codes. The existing Hamming code method has limitations as it requires more redundant bits and can only correct single or double errors. The proposed method uses a low-cost matrix code for error detection that can detect and locate multiple errors with lower area and delay overhead compared to existing complex error correction codes. Simulation results show the proposed scheme improves reliability against large multiple bit upsets in memory.

Uploaded by

sree anugraphics
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 23

SREE RAMA EDUCATIONAL SOCIETY GROUP OF INSTITUTIONS

Detecting And Correccting Multiple Bit


Upsets In Static Random Access Momoies

Presented By
Under The Guidence Of
A. Rupavathi
K.Yogitha Bali
14JE1D5703
M.Tech
M.TECH (VLSI)
Assistant Professor[ECE]
LIST OF CONTENTS
Abstract
Introduction
Existing Method
Demerits
Proposed Method
Merits
Applications
Tools
Results & Block Diagram
Conclusion
ABSTRACT
 Now a days to maintain good level of reliability, it is necessary to

protect memory bits using protection codes, for this purpose, various
error detection and correction methods are being used.
 The only drawback of the existing method is that more redundant bits

are required to maintain higher reliability of memory.


 Recently, error-detection code based on Hamming codes have been

proposed for memory protection.


 The main issue is that they are double error correction codes and the

error correction capabilities are not improved in all cases.


.

 In this paper, low-cost error-detection code based on divide-symbol

is proposed to enhance memory reliability with lower delay


overhead.

 The proposed technique used matrix code to assure reliability in

presence of multiple bit upset and reduce more redundant bit and its
correct more error compare to existing system.
INTRODUCTION
 1

 The soft error rate in memory cells is rapidly increasing, especially


when memories operate in space environments due to ionizing effects
of atmospheric neutron, alpha-particle, and cosmic rays.

 Although single bit upset is a major concern about memory reliability,


Multiple Bit Upset (MBUs) have become a serious reliability concern
in some memory applications.

 In order to make memory cells as fault-tolerant as possible, some


error correction codes (ECCs) have been widely used to protect
memories against soft errors for years.
.

 For example, the Bose–Chaudhuri–Hocquenghem codes, Reed–

Solomon codes, and Hamming codes have been used to deal with
MBUs in memories.

 But these codes require more area, power, and delay overheads since

the encoding and decoding circuits are more complex in these


complicated codes.
EXISTING METHOD

Block diagram of hamming encoder and decoder


.

 Hamming codes can detect and correct single-bit errors. In other

words, the hamming distance between the transmitted and received


code-words must be zero or one for reliable communication.
 Alternatively, it can detect (but not correct) up to two simultaneous

bit errors.
 To prevent MBUs from causing data corruption more complex error

correction codes are widely used to protect memory.


 The main issue is that they are double error correction codes and the

error correction capabilities are not improved in all the cases.


DEMERITS
 To prevent MBUs from causing data corruption, more complex error

correction codes (ECCs) are widely used to protect memory, but the
main problem is that they would require higher delay and area
overhead.

 The main issue is that they are double error correction codes and the

error correction capabilities are not improved in all cases.


PROPOSED METHOD
 In this paper, low-cost error-detection code based on Matrix code is

proposed to enhance memory reliability with lower delay overhead.

 The proposed low-cost error-detection code algorithm to obtain the

maximum error detection capability.

 Moreover, the parity-based erasure codes is proposed to minimize

the area overhead of extra circuits without disturbing the whole


encoding and decoding processes.
PROPOSED SCHEMATIC OF ENCODING AND DECODING
OF ERASURE CODES

Encoding and decoding of erasure codes


32-bits matrix logical organization (k = 2 × 4 and m = 4). Here,
each symbol is regarded as a matrix integer
PROPOSED ENCODER
 The horizontal redundant bits H can be obtained by matrix integer addition

as follows:

 H4H3H2H1H0 = D3D2D1D0 + D11D10D9D8 (1)

 H9H8H7H6H5 = D7D6D5D4 + D15D14D13D12 (2)

 and similarly for the horizontal redundant bits H14H13H12H11H10 and

H19H18H17H16H15, where “+” represents matrix integer addition.

 For the vertical redundant bits V, we have

 V0 = D0 ^ D16 (3)

 V1 = D1 ^ D17 (4)
PROPOSED DECODER
 ∆H4H3H2H1H0 = H4H3H2H1H0’ − H4H3H2H1H0 (5)
 S0 = V0’ ^ V0 (6)
 When ∆H4H3H2H1H0 and S3 − S0 are equal to zero, the stored

code word has original information bits in symbol 0 where no errors


occur. When ∆H4H3H2H1H0 and S3 − S0 are nonzero, the induced
errors (the number of errors is 4 in this case) are detected and located
in symbol 0, and then these errors can be corrected by
 D0correct = D0 ^ S0 (7)
ADVANTAGES
 Reduce the delay : the number of parity bits increases, the performance

of the Multi Bit Upset correction technique increases, it reduces the delay.

 Decrease the Area : the erasure codes is proposed to minimize the area

overhead of extra circuits (encoder and decoder) without disturbing the


whole encoding and decoding processes.

 Decreases the cost : configuration frame has to be equipped with a low-

cost error detection code. Once an error is detected, by assuming that the
erroneous frame is erased, its contents are recovered using an erasure
code.
APPLICATIONS
 Computer memories: the codes used are extended low-cost error-

detection the latter being perfect single-error-correcting.

 Photographs from spacecraft: the codes initially used were low-

cost error-detection, which can be constructed as the orthogonal


extended Hamming codes.

 Compact discs: the codes used are low-cost error-detection,

constructed using certain finite fields of large prime-power order.


TOOLS

TOOLS: Modelsim 6.3 for Debugging and Xilinx


14.3 for Synthesis and Hard Ware Implementation.
RESULTS
BLOCK DIAGRAM
RTL Schematic
TECHNOLOGY SCHEMATIC
SIMULATION OUTPUT WAVEFORM
CONCLUSION
In this paper, novel per-word was proposed to assure the reliability of
memory. The proposed protection code utilized algorithm to detect
errors, so that more errors were detected and corrected. The obtained
results showed that the proposed scheme has a superior protection level
against large MBUs in memory. Besides, the proposed error detection
technique is an attractive opinion to detect MBUs in CAM because it
can be combined with BICS to provide an adequate level of immunity.
.

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