VHDL 2

Identifiers, data objects and data types

Chapter2

Data
Identifiers objects Data types

constants Signals Variables

VHDL 2. Identifiers, data objects

and data types ver.0a 1
Identifiers
It is about how to create names

 Used to represent
Chapter2
an object
(constant, signal
or variable)
Data
Identifiers objects Data types

constants Signals Variables

VHDL 2. Identifiers, data objects

and data types ver.0a 2
Rules for Identifiers
 Names for users to identify data
objects: signals, variables etc.
 First character must be a letter
 last character cannot be an underscore
 Not case sensitive
 Two connected underscores are not
allowed
 Examples of identifiers: a, b, c, axy,
clk ...
VHDL 2. Identifiers, data objects
and data types ver.0a 3
Example:
a,b,equals are Identifiers of signals

 1 entity eqcomp4 is
 2 port (a, b: in std_logic_vector(3 downto 0);
 3 equals: out std_logic);
 4 end eqcomp4;
 5
 6 architecture dataflow1 of eqcomp4 is
 7 begin
 8 equals <= '1' when (a = b) else '0’;
 9-- “comment” equals is active high
 10 end dataflow1;

VHDL 2. Identifiers, data objects

and data types ver.0a 4
Data objects

VHDL 2. Identifiers, data objects

and data types ver.0a 5
Data objects
 Constant
Chapter2
 Signals
 variables
Data
Identifiers objects Data types

Constants Signals Variables

(Global) (Global) (Local)

VHDL 2. Identifiers, data objects

and data types ver.0a 6
Data objects: 3 different objects
 1 Constants: hold values that cannot be
changed within a design.
 e.g. constant width: integer :=8
 2 Signals: to represent wire connections
 e.g. signal count: bit_vector (3 downto 0)
 -- count means 4 wires; they are
count(3),count(2), count(1), count(0).
 3 Variables: internal representation used
by programmers; do not exist physically.

VHDL 2. Identifiers, data objects

and data types ver.0a 7
 Recall:
if a signal is used as input/output
declared in port

 It has 4 modes e.g.

entity eqcomp4 is
port (a, b: in std_logic_vector(3 downto 0 );
equals: out std_logic);
end eqcomp4;
Modes in port

IN out inout buffer

VHDL 2. Identifiers, data objects

and data types ver.0a 8
Syntax to create data objects

In entity declarations

VHDL 2. Identifiers, data objects

and data types ver.0a 9
Constants with initialized values
 constant CONST_NAME: <type_spec> :=
<value>;
 -- Examples:
 constant CONST_NAME: BOOLEAN := TRUE;
 constant CONST_NAME: INTEGER := 31;
 constant CONST_NAME: BIT_VECTOR (3 downto
0) := "0000";
 constant CONST_NAME: STD_LOGIC := 'Z';
 constant CONST_NAME: STD_LOGIC_VECTOR (3
downto 0) := "0-0-"; -- ‘-’ is don’t care

VHDL 2. Identifiers, data objects

and data types ver.0a 10
Signals with initialized values
 signal sig_NAME: type_name [: init. Value];
 -- examples
 signal s1_bool : BOOLEAN; -- no initialized value
 signal xsl_int1: INTEGER :=175;
 signal su2_bit: BIT :=‘1’;

VHDL 2. Identifiers, data objects

and data types ver.0a 11
Variables with initialized values
 variable V_NAME: type_name [: init. Value];
 -- examples
 variable v1_bool : BOOLEAN:= TRUE;
 variable val_int1: INTEGER:=135;
 variable vv2_bit: BIT; -- no initialized value

VHDL 2. Identifiers, data objects

and data types ver.0a 12
Signal and variable assignments

 SIG_NAME <= <expression>;

 VAR_NAME :=<expression>;

VHDL 2. Identifiers, data objects

and data types ver.0a 13
 Exercise 2.1: Find identifiers, I/O signals, variables,
constants, arrays, and list their data_types.
 1-- 4-bit parallel load register with asynchronous reset
 2-- CLK, ASYNC ,LOAD, : in STD_LOGIC;
 3-- DIN: in STD_LOGIC_VECTOR(3 downto 0);
 4-- DOUT: out STD_LOGIC_VECTOR(3 downto 0);
 5 process (CLK, ASYNC)
 6 begin
 7 if ASYNC='1' then
 8 DOUT <= "0000";
 9 elsif CLK='1' and CLK'event then
 10 if LOAD='1' then
 11 DOUT <= DIN;
 12 end if;
 13 end if;
 14 end process VHDL 2. Identifiers, data objects
and data types ver.0a 14
Data types
 Different types of wires
 Each type has a certain range of
logic levels

VHDL 2. Identifiers, data objects

and data types ver.0a 15
Data types

Chapter2

Data
Identifiers objects Data types

Constants Signals Variables

(Global) (Global) (Local)

VHDL 2. Identifiers, data objects

and data types ver.0a 16
Data types
 User can design the type for a data
object.
 E.g. a signal can have the type ‘bit’
 E.g. a variable can have the type ‘type
std_logic’
 Only same type can interact.

VHDL 2. Identifiers, data objects

and data types ver.0a 17
Types must match
Different types :
 1 entity test is port ( bit and std_logic
 2 in1: in bit;
 3 out1: out std_logic );
 4 end test;
 5 architecture test_arch of test is
 6 begin
 7 out1<=in1;
 8 end test_arch;
VHDL 2. Identifiers, data objects
and data types ver.0a 18
Exercise 2.2:
declare a signal “signx” with type bit in line 2

 1 Architecture test2_arch of test2

 2 ???????????
 3 begin
 4 ...
 5 …
 6 end test_arch

VHDL 2. Identifiers, data objects

and data types ver.0a 19
 Exercise 2.3: Where to specify the types for signals.
Draw the schematic of this circuit.

 1 entity nandgate is Specify types of signals in either

 2 port (in1, in2: in STD_LOGIC; (a) port declaration, or
 3 out1: out STD_LOGIC); (b) before ‘begin’ in architecture
 4 end nandgate; body
 5 architecture nandgate_arch of nandgate is
 6 signal connect1: STD_LOGIC;
 7 begin
 8 connect1 <= in1 and in2;
 9 out1<= not connect1;
 10 end nandgate_arch;

VHDL 2. Identifiers, data objects

and data types ver.0a 20
Revision (so far we learned)
 Data object
 Constants, signal, Chapter2
Variables
 Signal in port
(external pins)
 In Data
 Out Identifiers objects Data types
 Inout
 Buffer
 Data type
 Many types: integer, Constants Signals Variables
float, bit, std_logic, (Global) (Global) (Local)
etc.

VHDL 2. Identifiers, data objects

and data types ver.0a 21
Worksheet 2.4:
Q1: What kinds of data objects “in1 and in2” belong to?
Q2: What is the data type and mode for “out1”?

Specify types of signals in either

 1 entity nandgate is (a) port declaration, or
 2 port (in1, in2: in STD_LOGIC;
(b) before ‘begin’ in architecture
 3 out1: out STD_LOGIC); body
 4 end nandgate;
 5 architecture nandgate_arch of nandgate is
 6 signal connect1: STD_LOGIC;
 7 begin
 8 connect1 <= in1 and in2;
 9 out1<= not connect1;
 10 end nandgate_arch;

VHDL 2. Identifiers, data objects

and data types ver.0a 22
Different data types

VHDL 2. Identifiers, data objects

and data types ver.0a 23
 Different data types
Chapter2

Enumeration:
Red, blue Data
standard logic: Boolean: Identifiers objects Data types

Resolved, “TRUE”,

Unresolved ”FALSE”
Constants Signals Variables
(Global) (Global) (Local)

Float: Bit:
Data types
0.124 0,1

Integer: Character
13234,23 ‘a’,’b’
String:
“text”

VHDL 2. Identifiers, data objects

and data types ver.0a 24
Examples of some common types
 Type BOOLEAN is (FALSE, TRUE)
 type bit is (‘0’ ,’1’);
 type character is (-- ascii string)
 type INTEGER is range of integer
numbers
 type REAL is range of real numbers

VHDL 2. Identifiers, data objects

and data types ver.0a 25
Boolean, Bit Types
 Boolean (true/false), character,
integer, real, string, these types have
their usual meanings. In addition,
VHDL has the types: bit, bit_vector,
 The type “bit” can have a value of '0' or
'1'. A bit_vector is an array of bits.
 See VHDL Quick Reference
http://www.doulos.com/knowhow/vhdl
_designers_guide/

VHDL 2. Identifiers, data objects

and data types ver.0a 26
Integer type (depends on your tool; it
uses large amount of logic circuits for
the implementation of integer/float
operators) E.g.

 Range from -(2^31-1) to (2^31-1)

VHDL 2. Identifiers, data objects

and data types ver.0a 27
Floating type
 -1.0E38 to 1.0E38
 For encoding floating numbers, but
usually not supported by synthesis
tools of programmable logic
because of its huge demand of
resources.

VHDL 2. Identifiers, data objects

and data types ver.0a 28
Enumeration types:
 How to input an abstract concept
into a circuit ?
 E.g.1 color: red, blue, yellow, orange
etc, we need 2 bits
 E.g.2
 Language type: Chinese, English,
Spanish, Japanese, Arabic. How
many bits needed?
 Answer: 5 different combinations: 3 bits

VHDL 2. Identifiers, data objects

and data types ver.0a 29
Enumeration types:
 An enumeration type is defined by
listing (enumerating) all possible values
 Examples:
 type COLOR is (BLUE, GREEN, YELLOW,
RED);
 type MY_LOGIC is (’0’, ’1’, ’U’,
’Z’);
 -- then MY_LOGIC can be one of
the 4 values

VHDL 2. Identifiers, data objects

and data types ver.0a 30
Exercises 2.5
 Declare an enumeration type of the
traffic light.
 Declare an enumeration type of the
outcome of rolling a dice.
 Declare an enumeration type of the
7 notes of music.

VHDL 2. Identifiers, data objects

and data types ver.0a 31
Define

Array or a bus

VHDL 2. Identifiers, data objects

and data types ver.0a 32
Std_logic_vector (array of bits) for
bus implementation bit
bit
Bit_vector
Bit_vector bit
 To turn bits into a bus bit
 ‘bit’ or ‘std_logic’ is ‘0’, ‘1’ etc.
 Std_logic_vector is “000111”etc.
 1 entity eqcomp3 is
 2 port (a, b: in std_logic_vector(2 downto 0);
 3 equals:out std_logic);
 4 end eqcomp3;
 So a, b are 3-bit vectors:
 a(2), a(1), a(0), b(2), b(1), b(0),

VHDL 2. Identifiers, data objects

and data types ver.0a 33
Exercise 2.6 ;Difference between
“to” and “downto”
 Given:
 signal a : std_logic_vector( 2 downto 0);
 Create a 3-bit bus c using “to”instead of
“downto” in the declaration.
 Draw the circuit for this statement: c<=a;

VHDL 2. Identifiers, data objects

and data types ver.0a 34
An advanced topic

Resolved, Unresolved logic

(Concept of Multi-value logic)

VHDL 2. Identifiers, data objects

and data types ver.0a 35
Resolved logic concept
(Multi-value Signal logic)
 Can the outputs be connected
together?

C1

??
C2

VHDL 2. Identifiers, data objects

and data types ver.0a 36
Resolved signal concept
 Signal c1,c2, b1: bit;

c1 b1
 b1<=c1;

VHDL 2. Identifiers, data objects

and data types ver.0a 37
 Resolved signal concept

 Signal c1,c2, b1: bit;

 b1<=C1; ?? C1 b1
 b1<=C2; illegal
??
C2

VHDL 2. Identifiers, data objects

and data types ver.0a 38
Type Std_logic and std_ulogic

 Std_logic is a type of resolved logic, that

means a signal can be driven by 2 inputs

 std_ulogic: (the “u”: means unresolved)

Std_ulogic type is unresolved logic, that
means a signal cannot be driven by 2
inputs

VHDL 2. Identifiers, data objects

and data types ver.0a 39
Although VHDL allows resolved types, but
Xilinx has not implemented it

 Error message # 400

 Signal 'name' has multiple drivers.
 The compiler has encountered a signal
that is being driven in more than one
process.
 Note that it is legal VHDL to have a signal
with multiple drivers if the signals type is
a resolved type (i.e. has a resolution
function) such as 'std_logic' (but not
'std_ulogic'). (Metamor, Inc.)

VHDL 2. Identifiers, data objects

and data types ver.0a 40
Standard logic type and
resolved logic (Multi-Value
Signal Types)

The IEEE_1164 library -- the

industrial standard And some of its
essential data types

VHDL 2. Identifiers, data objects

and data types ver.0a 41
To use the library, add the two
lines at the front
 Library IEEE
 use IEEE.std_logic_1164.all
 entity

 architecture

VHDL 2. Identifiers, data objects

and data types ver.0a 42
The 9-valued logic standard logic system of
IEEE_1164, It specifies the possible states of a
signal(Multi-Value Signal Types)

 ‘U’ Uninitialized
 ‘X’ Forcing Unknown
 ‘0’ Forcing 0
 ‘1’ Forcing 1
 ‘Z’ High Impedance=float ?
 ‘W’ Weak Unknown state
 ‘L’ Weak 0
 ‘H’ Weak 1
 ‘-’ Don’t care

VHDL 2. Identifiers, data objects

and data types ver.0a 43
Resolved rules of the 9-level logic
 There are weak unknown, weak 0, weak
1 and force unknown, force 0, force 1
 when 2 signals tight together, the
forcing signal dominates.
 It is used to model the internal of a
device.
 In our applications here, the subset
of the IEEE forcing values ‘X’ ‘0’ ‘1’
‘Z’ are used.

VHDL 2. Identifiers, data objects

and data types ver.0a 44
Exercise 2.7:Resolution table when two
std_logic signals S1,S2 meet
(X=forcing unknown, Z=float)

 Fill in the blanks “?”

S1=X S1=0 S1=1 S1=Z
X X X X S2=X
X 0 X 0 S2=0
X ? ? ? S2=1
X ? ? ? S2=Z
VHDL 2. Identifiers, data objects
and data types ver.0a 45
 From:
http://zeus.phys.uconn.edu/wiki/index.p
hp/VHDL_tutorial

VHDL Resolution Table

U X 0 1 Z W L H –
U U U U U U U U U U
‘U’ Uninitialized
‘X’ Forcing Unknown X U X X X X X X X X
‘0’ Forcing 0 0 U X 0 X 0 0 0 0 X
‘1’ Forcing 1 1 U X X 1 1 1 1 1 X
‘Z’ Float Z U X 0 1 Z W L H X
‘W’ Weak Unknown
‘L’ Weak 0
W U X 0 1 W W W W X
‘H’ Weak 1 L U X 0 1 L W L W X
‘-’ Don’t care H U X 0 1 H W W H X

VHDL 2. Identifiers, data objects

and data types ver.0a 46
 Appendix 1
Example of using IEEE1164


library
libraryIEEE;
IEEE;
use
useIEEE.std_logic_1164.all;
IEEE.std_logic_1164.all; ----defines
definesstd_logic
std_logictypes
types
--library
--librarymetamor;
metamor;

entity
entityjcounter
jcounterisis
port
port((
clk
clk: :ininSTD_LOGIC;
STD_LOGIC;
qq: :buffer
bufferSTD_LOGIC_VECTOR
STD_LOGIC_VECTOR(7(7downto
downto0)0)
););
VHDL 2. Identifiers, data objects
and data types ver.0a 47
Quick Revision
 You should have learnt
 Identifier and usage
 Different data objects (constant,
signals, variables)
 Different data types (Boolean , integer
etc)
 Resolved logic

VHDL 2. Identifiers, data objects

and data types ver.0a 48