Microprocessor and

Assembly Language
Programming

8085 Microprocessor
Architecture

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Intel 8085 CPU Block Diagram

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 The 8085 Block Diagram
 Registers – hold temporary data.
 Instruction register (IR)– holds the currently
executing instruction.
 Instruction Decoder (ID)- decodes the
instruction. Once decoded, the instruction
controls the remainder of the MPU, memory
and IO through the timing and control block.

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 The 8085 Block Diagram
 Temporary register- holds information from the
memory or register array. An input of the ALU.
 Increment/Decrement address latch – It adds
or subtracts one from any of other registers in
register array.

Why are the PC and SP registers are 16-bit ?

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Signals and I/O Pins
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Intel 8085 Pin

Configuration

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 Clock Pins
 8085 MPU has 3 pins
that control or
present the clock 8085A
signal.
 X1 and X2 pins
determine the X1 CLK OUT
clock frequency. 6 MHz
 CLK OUT is a TTL X2
square-wave
output clock.
 The CLOCK OUT is
one-half the
crystal frequency.

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 8085 Pinout
 8085 μp consists of 16 signal pins use as address
bus.
 Divide into 2 part: A15 – A8 (upper) and
AD7 – AD0 (lower).
 A15 – A8 : Unidirectional, known as ‘high order
address’.
 AD7 – AD0 : bidirectional and dual purpose
(address and data placed once at a time).
 AD7 – AD0 also known as ‘low order address’.
 To execute an instruction, at early stage AD7 –
AD0 uses as address bus and alternately as
data bus for the next cycle.
 The method to change from address bus to
data bus known as ‘bus multiplexing’.

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 8085 Pinout

 Group of signals consists of :

 Two control signals (‘RD’ – read; and ‘WR’ -
write).
 Three status signals (IO/M, S1, and S0) to
recognize nature of operation.
 ALE (Address Latch Enable) signal :
 active high signal - generated to show the

start of 8085 operation.

 When transition 1-to-0: indicate that lines

AD7-AD0 (AD7-AD0 = A7-A0) act as address

lines.

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ALE used to demultiplex address/data bus

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 Control
Control and
and Status
Status Signals
Signals
 Signals:
 RD – Read (active low). To indicate that the I/O or
memory selected is to be read and data are available on
the bus.
 WR – Write: Active low. This is to indicate that the data
available on the bus are to be written to memory or I/O
ports.
 IO/M – To differentiate I/O operation of memory
operations.
 ‘0’ - indicates a memory operation.

 ‘1’-indicates an I/O operation.

 IO/M combined with RD and WR to generate I/O and

memory control signals.
 S1 dan S0: Status signals, similar to IO/M, can identify
various operations as shown on the following table :

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Control
Control and
and Status
Status Signals.
Signals.

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 Interrupt
Interrupt Signals
Signals
 8085 μp has several interrupt signals as shown in the following
table.

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 Interrupt
Interrupt signals
signals
 An interrupt is a hardware-initiated subroutine CALL.
 When interrupt pin is activated, an ISR will be
called, interrupting the program that is currently
executing.
Pin Subroutine Location
TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
INTR *
Note: * the address of the ISR is determined by the external hardware.

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 Interrupt
Interrupt signals
signals

 INTR input is enabled when EI instruction

is executed.
 The status of the RST 7.5, RST 6.5 and
RST 5.5 pins are determined by both EI
instruction and the condition of the mask
bits in the interrupt mask register.

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Interrupt
Interrupt
Vectors
Vectors

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 A
A circuit
circuit that
that causes
causes an
an RST4
RST4 instruction
instruction (E7)
(E7)
to
to be
be executed
executed inin response
response to
to INTR.
INTR.

 When INTR is
asserted,
8085
response with
INTA pulse.
 During INTA
pulse, 8085
expect to see
an instruction
applied to its
data bus.

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 RESET
RESET signal
signal

 Following are the two kind of RESET signals:

 RESET IN: an active low input signal, Program
Counter (PC) will be set to 0 and thus MPU will
reset.
 RESET OUT: an output reset signal to indicate that
the μp was reset (i.e. RESET IN=0). It also used to
reset external devices.

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RESET
RESET signal
signal

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 Direct
Direct Memory
Memory Access
Access (DMA)
(DMA)
 DMA is an IO technique where external IO
device requests the use of the MPU buses.
 Allows external IO devices to gain high speed
access to the memory.
 Example of IO devices that use DMA: disk memory
system.
 HOLD and HLDA are used for DMA.
 If HOLD=1, 8085 will place it address, data and
control pins at their high-impedance.
 A DMA acknowledgement is signaled by
HLDA=1.

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 MPU
MPU Communication
Communication and
and Bus
Bus Timing
Timing

Figure 3: Moving data form memory to MPU using instruction MOV C, A

(code machine 4FH = 0100 1111)
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MPU
MPU Communication
Communication and
and Bus
Bus Timing
Timing
 The Fetch Execute Sequence :
1. The μp placed a 16 bit memory address from PC
(program counter) to address bus.
– Figure 4: at T1
– The high order address, 20H, is placed at A15 – A8.
– the low order address, 05H, is placed at AD7 - AD0
and ALE is active high.
– Synchronously the IO/M is in active low condition to
show it is a memory operation.
2. At T2 the active low control signal, RD, is
activated so as to activate read operation; it is to
indicate that the MPU is in fetch mode operation.

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 MPU
MPU Communication
Communication and
and Bus
Bus Timing
Timing

Figure 4: 8085 timing diagram for Opcode fetch cycle for MOV C, A .
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MPU
MPU Communication
Communication and
and Bus
Bus Timing
Timing
3. T3: The active low RD signal enabled the byte
instruction, 4FH, to be placed on AD7 – AD0
and transferred to the MPU. While RD high,
the data bus will be in high impedance mode.
4. T4: The machine code, 4FH, will then be
decoded in instruction decoder. The content
of accumulator (A) will then copied into C
register at time state, T4.

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 8085
8085 Microprocessor
Microprocessor
Architecture
Architecture –
–
Demultiplexing
Demultiplexing the
the AD7-
AD7-
AD0
AD0
 Bus
Bus Demultiplexer
Demultiplexer AD
AD77-AD
-AD00
 It is necessary to have the knowledge and
skills to demultiplex data bus and address
bus as it is important in hardware design
applications.
 Like previous example (referring to timing
diagram): MOV C,A => with machine code
(4FH)

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 Bus
Bus Demultiplexer
Demultiplexer AD
AD77-AD
-AD00

Figure 1

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 Bus
Bus Demultiplexer
Demultiplexer AD
AD77-AD
-AD00
 From fig 1, to run instruction MOV C, A the
high order address bus maintained as bus
address for three clock periods.
 However the low order address bus (05H)
was eliminated after first time state.
 The address need to be latched as to
identify memory address.
 After T1, the bus AD7-AD0 now becomes
4FH.

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 Schematic diagram to latch low order address
bus.

05H

Figure 2

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 Bus
Bus Demultiplexer
Demultiplexer AD
AD77-AD
-AD00
 In Fig 2, the AD7-AD0 bus is connected to the
input of latch buffer 74LS373.
 The ALE signal is connected to enable pin (G) at
latch, and the output control signal is grounded
(OC).
 When the ALE signal is active high, the latch will
act according to the input instruction (the output
changes according to input data).
 At T1 the latch output value is 05H, and when ALE
is low, the byte data 05H is hold until the new
next ALE signal activated.
 This causes the output latch is low order address
memory A7-A0 (05H).
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 Control
Control Signals
Signals

 It is necessary to generate two RD control

signals, one for memory and one for
peripheral.
 Similar to WR control signal; one for
writing to memory and one for writing to
output peripheral.

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 Control
Control Signals
Signals

Figure 3: Example of schematic diagram to generate control

signals.
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Control
Control Signals
Signals and
and Demultiplexing
Demultiplexing

Figure 4:the
combination of
control signals
as well as
demultiplexing
the bus system.

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Thank
you
Q&A

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