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Lecture 1-VHDL

VHDL is a hardware description language used to model digital systems. It allows designers to specify both the structure and behavior of a digital system, and supports design simulation, synthesis, and documentation. The key elements of a basic VHDL design include an entity declaration to define the inputs and outputs, and an architecture body containing concurrent statements to describe the design's internal logic and behavior.

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Sultanus Salehin ,152431
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69 views

Lecture 1-VHDL

VHDL is a hardware description language used to model digital systems. It allows designers to specify both the structure and behavior of a digital system, and supports design simulation, synthesis, and documentation. The key elements of a basic VHDL design include an entity declaration to define the inputs and outputs, and an architecture body containing concurrent statements to describe the design's internal logic and behavior.

Uploaded by

Sultanus Salehin ,152431
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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VHDL Introduction

VHDL Introduction
V- VHSIC
 Very High Speed Integrated Circuit
H- Hardware
D- Description
L- Language
VHDL Benefits
1. Public Standard
2. Technology and Process Independent
 Include technology via libraries
3. Supports a variety of design methodologies
1. Behavioral modeling
2. Dataflow or RTL (Register Transfer Language)
Modeling
3. Structural or gate level modeling
VHDL Benefits (cont)
4. Supports Design Exchange
 VHDL Code can run on a variety of
systems
5. Supports Design Reuse
 Code “objects” can be used in multiple
designs
6. Supports Design Hierarchy
 Design can be implemented as interconnected
submodules
VHDL Benefits (cont)
7. Supports Synchronous and Asynchronous Designs
8. Supports Design Simulation
 Functional (unit delay)
 Timing (“actual” delay)
9. Supports Design Synthesis
 Hardware implementation of the design obtained directly from
VHDL code.

10. Supports Design Documentation


 Original purpose for VHDL – Department of Defense
VHDL Design Units
Entity Declaration
 Describes external view of the design (e.g. I/O)
Architecture Body (AB)
 Describes internal view of the design
Configuration Declaration
Package Declaration
 Library Declaration
Package Body
Architecture Body (AB)
The architecture body contains the internal
description of the design entity. The VHDL
specification states that a single design entity can
contain multiple architecture bodies. Each AB can
be used to describe the design using a different
level of abstraction.
VHDL Statement Terminator
Each VHDL Statements is terminated
using a semicolon

;
VHDL Comment Operator
To include a comment in VHDL, use the
comment operator

-- This is a comment
-- This is an example of a comment
y <= 0; -- can occur at any point
Signal Assignment Operator
To assign a value to a signal data object
in VHDL, we use the
signal assignment operator

<=
Example:

y <= ‘1’; -- signal y is assigned the value ONE


VHDL Syntax
VHDL Syntax – Entity Declaration
Describes I/O of the design. I/O Signals
are called ports.
The syntax is:

Entity design_name is

port(signal1,signal2,…..:mode type;
signal3,signal4,…..:mode type);

End entity design_name;


VHDL Syntax – Entity Example
Entity my_example is
port( a,b,c: in std_logic;
s: in std_logic_vector(1 downto 0);
e,f: out std_logic;
y: out std_logic_vector(4 downto 0));
end entity my_example;

Maxplus II Block Diagram


Architecture Body Syntax
Architecture name of entity_name is
internal signal and constant declarations
Begin
Concurrent statement 1;
Concurrent statement 2;
Concurrent statement 3;
Concurrent statement 4;
End architecture name;
VHDL Program Template
Library altera; Architecture name of entity_name is
Use altera.maxplus2.all; internal signal and constant
declarations
Library ieee;
Begin
Use ieee.std_logic_1164.all;
Concurrent statement 1;
Use ieee.std_logic_arith.all; Concurrent statement 2;
Concurrent statement 3;
Entity design_name is
port(signal1,signal2,…..:mode type; Concurrent statement 4;
signal3,signal4,…..:mode type); End architecture name;
End entity design_name;

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