COMPUTER ORGANIZATION

AND ARCHITECTURE

UNIT - I
Digital Computers:
Introduction
Block diagram of Digital Computer
Definition of Computer Organization
Computer Design and Computer
Architecture.
Introduction
Block diagram of Digital Computer
 Figure shows the general structure of the computer. It consists of:
• A main memory, which stores both data and instructions.
• An arithmetic-logical unit (ALU) capable of operating on binary data.
• A control unit, which interprets the instructions in memory and causes them to be executed.
• Input and output (I/O) equipment operated by the control unit.
Computer Architecture
Computer architecture refers to those attributes of a system visible to a
programmer, or put another way, those attributes that have a direct impact on the
logical execution of a program.

Computer Architecture is a functional description of requirements and design

implementation for the various parts of computer.It deals with functional behavior of
computer system. It comes before the computer organization while designing a
computer.
Architecture describes what the computer does.

Examples of architecture attributes include the instruction set, the number of bit to
represent various data types (e.g.., numbers, and characters), I/O mechanisms, and
technique for addressing memory.
Definition of Computer Organization
Computer organization refers to the operational units and their interconnection that
realize the architecture specification.

Examples of organization attributes include those hardware details transparent to

the programmer, such as control signals, interfaces between the computer and
peripherals, and the memory technology used.

As an example, it is an architectural design issue whether a computer will have a

multiply instruction. It is an organizational issue whether that instruction will be
implemented by a special multiply unit or by a mechanism that makes repeated use of
the add unit of the system. The organization decision may be bases on the anticipated
frequency of use of the multiply instruction, the relative speed of the two approaches,
and the cost and physical size of a special multiply unit.

  Many computer manufacturers offer the family of computer models, all of the
same architecture but with differences in organization. Computer Architecture may
remain for several years but organization changes with changing technology.
 Computer Organization comes after the decide of Computer Architecture first.
Computer Organization is how operational attribute are linked together and contribute
to realise the architectural specification. Computer Organization deals with structural
relationship.
Organization describes how it does it.
Computer Design and Computer Architecture
Computer Design
Computer design is concerned with the hardware design of the computer. Once the
computer specifications are formulated, it is the task of the designer to develop
hardware for the system.

Computer design is concerned with the determination of what hardware should be

used and how the parts should be connected. This aspect of computer hardware is
sometimes referred to as computer implementation.

Computer Architecture
Computer architecture is concerned with the structure and behavior of the
computer as seen by the user. It includes the information formats, the instruction set,
and techniques for addressing memory.

The architectural design of a computer system is concerned with the specifications

of the various functional modules, such as processors and memories, and structuring
them together into a computer system.
 Computer Architecture Computer Organization
Computer Architecture is concerned with Computer Organization is concerned with
the way hardware components are the structure and behaviour of a computer
connected together to form a computer system as seen by the user.
system.
It acts as the interface between hardware It deals with the components of a
and software. connection in a system.
Computer Architecture helps us to Computer Organization tells us how
understand the functionalities of a system. exactly all the units in the system are
arranged and interconnected.
A programmer can view architecture in Whereas Organization expresses the
terms of instructions, addressing modes realization of architecture.
and registers.
While designing a computer system An organization is done on the basis of
architecture is considered first. architecture.
Computer Architecture deals with high- Computer Organization deals with low-
level design issues. level design issues.
Architecture involves Logic (Instruction Organization involves Physical
sets, Addressing modes, Data types, Cache Components (Circuit design, Adders,
optimization) Signals, Peripherals)
Register Transfer Language and Micro operations:

Register Transfer language

Register Transfer
Bus and memory transfers
Arithmetic Micro operations
Logic micro operations
Shift micro operations
Arithmetic logic shift unit.

11
• Simple digital systems are frequently characterized in terms of
– the registers they contain
– the operations that they perform
– the control that initiates the sequence of microoperations

• Digital Module= Registers + Microoperations Hardware + Control Functions

• Typically,
– What operations are performed on the data in the registers
– What information is passed between registers
MICRO OPERATIONS
• The operations on the data stored in registers are called micro operations.

• It is an elementary operation performed on the information stored in one or more

registers.

• The result of micro operation may replace the previous information of a register or
may be transformed to another register.

• The functions built into registers are examples of micro operations

– Shift
– Load
– Clear
– ‹Increment
– Add
– Subtract
– Complement
– ….
 Cont..

• For any function of the computer, a sequence of micro operations is used to

describe it
• The result of the operation may be:
– replace the previous binary information of a register or
– transferred to another register

Shift Right
101101110011 010110111001
Operation
Register Transfer Language
Register Transfer Language (RTL) :

• A symbolic notation to describe the micro operation transfers among registers

• A convenient tool for describing the internal organization of digital computers

• ‹Can also be used to facilitate the design

Register Transfer
• Computer registers are designated by capital letters (sometimes followed by
numerals) to denote the function of the register

• R1: processor register

• MAR: Memory Address Register (holds an address for a memory unit)
• PC: Program Counter
• IR: Instruction Register
• SR: Status Register
Register Transfer cont.
• The individual flip-flops in an n-bit register are numbered in sequence from 0 to n-
1 (from the right position toward the left position)

R1 7 6 5 4 3 2 1 0

Register R1 Showing individual bits

A block diagram of a register

Register Transfer cont.

Other ways of drawing the block diagram of a register:

15 0
PC

Numbering of bits

15 87 0
Upper byte PC(H) PC(L) Lower byte
Partitioned into two parts

18
Register Transfer cont.
• Information transfer from one register to another is described by a replacement
operator:
R2 ← R1

• This statement denotes a transfer of the content of register R1 into register R2

• The transfer happens in one clock cycle

• The content of the R1 (source) does not change

• The content of the R2 (destination) will be lost and replaced by the new data
transferred from R1

• Assuming that the circuits are available from the outputs of the source register to
the inputs of the destination register, and that the destination register has a parallel
load capability
Register Transfer cont.
• Transfer to occur only under a predetermined control condition

• This can be shown by means of if-then statement

if (P=1) then R2 ← R1

• Representation of a (conditional) transfer

P: R2 ← R1

• A binary condition (P equals to 0 or 1) determines when the transfer occurs

• The content of R1 is transferred into R2 only if P is 1

Register Transfer cont.

Hardware implementation of a controlled transfer:

P: R2 ← R1

Block diagram: Control P Load

R2 Clock
Circuit

R1

t t+1

Timing diagram
Clock
Synchronized
Load
with the clock
Transfer occurs here
Register Transfer cont.

Basic Symbols for Register Transfers

Symbol Description Examples

Letters & numerals Denotes a register MAR, R2

Parenthesis ( ) Denotes a part of a register R2(0-7), R2(L)

Arrow ← Denotes transfer of information R2 ← R1

Comma , Separates two microoperations R2 ← R1, R1 ← R2

Bus and Memory Transfers
• Paths must be provided to transfer information from one register to another

• A Common Bus System is a scheme for transferring information between registers

in a multiple-register configuration

• A bus: set of common lines, one for each bit of a register, through which binary
information is transferred one at a time

• Control signals determine which register is selected by the bus during each
particular register transfer
Bus and Memory Transfers

Register A Register B Register C Register D

Bus lines

Register D Register C Register B Register A

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

D3 D2 D1 D0 C3 C2 C1 C0 B3 B2 B1 B0 A3 A2 A1 A0

D3 C3 B3 A3 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0

3 2 1 0 3 2 1 0 3 2 1 0
3 2 1 0 S0
S0 S0 S0
MUX3 MUX2 MUX1 MUX0 S1
S1 S1 S1

4-Line Common Bus

Bus and Memory Transfers
• The transfer of information from a bus into one of many destination registers is
done:
– By connecting the bus lines to the inputs of all destination registers and then:
– activating the load control of the particular destination register selected

R2 ← C
• to symbolize that the content of register C is loaded into the register R2
using the common system bus

• It is equivalent to:
BUS ←C, (select C)
R2 ←BUS (Load R2)
Bus and Memory Transfers:
Three-State Bus Buffers
• A bus system can be constructed with three-state buffer gates instead of
multiplexers

• A three-state buffer is a digital circuit that exhibits three states: logic-0, logic-1, and
high-impedance (Hi-Z)
Control input C

Normal input A Output B

Three-State Buffer
Bus and Memory Transfers:
Three-State Bus Buffers cont.

C=1

Buffer
A B A B

C=0

Open Circuit
A B A B
Bus and Memory Transfers:
Three-State Bus Buffers cont.

S1 0
Select
S0 1
Bus line for bit 0
2×4 A0
Decoder 2
Enable E
3

B0

C0

D0

Bus line with three-state buffer (replaces MUX0 in the previous diagram)
Bus and Memory Transfers:
Memory Transfer
• Memory read : Transfer from memory

• Memory write : Transfer to memory

• Data being read or wrote is called a memory word (called M)

• It is necessary to specify the address of M when writing /reading memory

• This is done by enclosing the address in square brackets following the letter M

• Example: M[0016] : the memory contents at address 0x0016

Bus and Memory Transfers: Memory Transfer cont.
• Assume that the address of a memory unit is stored in a register called the Address
Register AR
• Lets represent a Data Register with DR, then:
• Read: DR ← M[AR]
• Write: M[AR] ← DR
Bus and Memory Transfers: Memory Transfer cont.

AR
x0C 19
x12 x0E 34
R1 x10 45
100 x12 66
x14 0
x16 13
R1←M[AR] x18 22

RAM

R1 R1
100 66
Arithmetic Micro operations
• The micro operations most often encountered in digital computers are classified
into four categories:
– Register transfer micro operations
– Arithmetic micro operations (on numeric data stored in the registers)
– Logic micro operations (bit manipulations on non-numeric data)
– Shift micro operations
Arithmetic Micro operations cont.
• The basic arithmetic microoperations are: addition, subtraction, increment,
decrement, and shift
• Addition Microoperation:
R3 ←R1+R2
• Subtraction Microoperation:
R3 ←R1-R2
1’s complement
or
R3 ←R1+R2+1
Arithmetic Micro operations cont.
• One’s Complement Micro operation:
R2 ←R2
• Two’s Complement Micro operation:
R2 ←R2+1
• Increment Micro operation:
R2 ←R2+1
• Decrement Micro operation:
R2 ←R2-1
Half Adder/Full Adder

Half Adder x y c s
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Full Adder
x y cn-1 cn s
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

x
y S
cn-1
cn
Arithmetic Micro operations Binary Adder

B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1
FA FA FA FA C0

C4 S3 S2 S1 S0

4-bit binary adder (connection of FAs)

Arithmetic Micro operations
Binary Adder-Subtractor

B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0

4-bit adder-subtractor
Arithmetic Micro operations
Binary Incrementer

A3 A2 A1 A0 1

x y x y x y x y

HA HA HA HA

C S C S C S C S

C4 S3 S2 S1 S0

4-bit Binary Incrementer

Arithmetic Micro operations
Binary Incrementer

• Binary Incrementer can also be implemented using a counter

• A binary decrementer can be implemented by adding 1111 to the desired register

each time!
Logic Micro operations
The four basic micro operations
OR Micro operation
• Symbol: , +

• Gate:

Example: 1001102  10101102 = 11101102

OR

P+Q: R1←R2+R3, R4←R5 R6

ADD
OR
Logic Microoperations
The four basic microoperations cont.
AND Micro operation

• Symbol: 

• Gate:

Example: 1001102  10101102 = 00001102

Logic Micro operations
The four basic micro operations cont.
Complement (NOT) Micro operation
• Symbol: 

• Gate:

Example: 10101102 = 01010012

Logic Micro operations
The four basic micro operations cont.

XOR (Exclusive-OR) Micro operation

• Symbol: 

• Gate:

Example: 1001102  10101102 = 11100002

Logic Micro operations
Other Logic Micro operations cont.
NAND Micro operation
• Symbols:  and 

• Gate:

Example: 1001102  10101102 = 11110012

Logic Micro operations
Other Logic Micro operations cont.
NOR Micro operation
• Symbols:  and 

• Gate:

Example: 1001102  10101102 = 00010012

Logic Micro operations
Other Logic Micro operations cont.

Set (Preset) Micro operation

• Force all bits into 1’s by ORing them with a value in which all its bits are being
assigned to logic-1

Example: 1001102  1111112 = 1111112

Clear (Reset) Micro operation

• Force all bits into 0’s by ANDing them with a value in which all its bits are being
assigned to logic-0

Example: 1001102  0000002 = 0000002

Logic Micro operations
Other Logic Micro operations cont.
Selective Set

Selective Complement
Selective Clear
Mask
Insert
Logic Micro operations
Hardware Implementation
• The hardware implementation of logic micro operations requires that logic gates be
inserted for each bit or pair of bits in the registers to perform the required logic
function

• Most computers use only four (AND, OR, XOR, and NOT) from which all others
can be derived.
Shift Micro operations
• Used for serial transfer of data

• Also used in conjunction with arithmetic, logic, and other data-processing

operations

• The contents of the register can be shifted to the left or to the right

• As being shifted, the first flip-flop receives its binary information from the serial
input

• Three types of shift:

 Logical,
 Circular,
 Arithmetic
Shift Micro operations cont.

Serial Input r2 Serial Output

rn-1 r3 r1 r0

Determines Shift Right

the “shift”
type

Serial Output Serial Input

rn-1 r3 r2 r1 r0

Shift Left

**Note that the bit ri is the bit at position (i) of the register
Shift Micro operations:
Logical Shifts
• Transfers 0 through the serial input

• Logical Shift Right: R1←shr R1

The same
• Logical Shift Left: R2←shl R2

The same

? rn-1 r3 r2 r1 r0 0

Logical Shift Left

Shift Micro operations:
Circular Shifts (Rotate Operation)
• Circulates the bits of the register around the two ends without loss of information
• Circular Shift Right: R1←cir R1

• Circular Shift Left: R2←cil R2 The same

The same

rn-1 r3 r2 r1 r0

Circular Shift Left

Shift Micro operations
Arithmetic Shifts
• Shifts a signed binary number to the left or right

• An arithmetic shift-left multiplies a signed binary number by 2:

ashl (00100): 01000

• An arithmetic shift-right divides the number by 2

ashr (00100) : 00010

• An overflow may occur in arithmetic shift-left, and occurs when the sign bit is
changed (sign reversal)
Shift Micro operations
Arithmetic Shifts cont.

rn-1 r3 r2 r1 r0
?
Sign
Bit Arithmetic Shift Right

? rn-1 r3 r2 r1 r0 0
Sign
Arithmetic Shift Left
Bit
Shift Micro operations
Arithmetic Shifts cont.

• An overflow flip-flop Vs can be used to detect an arithmetic shift-left overflow

Vs = Rn-1  Rn-2

Rn-1 1  overflow
Vs=
Rn-2 0  no overflow
Shift Micro operations cont.
Example: Assume R1=11001110, then:

Arithmetic shift right once : R1 = 11100111

Arithmetic shift right twice : R1 = 11110011

Arithmetic shift left once : R1 = 10011100

Arithmetic shift left twice : R1 = 00111000

Logical shift right once : R1 = 01100111

Logical shift left once : R1 = 10011100

Circular shift right once : R1 = 01100111

Circular shift left once : R1 = 10011101

Shift Microoperations
Hardware Implementation cont.

• A possible choice for a shift unit would be a bidirectional shift register with parallel
load has drawbacks:
– Needs two pulses (the clock and the shift signal pulse)
– Not efficient in a processor unit where multiple number of registers share a
common bus
• It is more efficient to implement the shift operation with a combinational circuit
Shift Microoperations
Hardware Implementation cont.

Serial Input IR Serial Input IL

A3 A2 A1 A0

Select
0 for shift right
S 1 0 S 1 0 S 1 0 S 1 0
1 for shift left
MUX MUX MUX MUX

H3 H2 H1 H0

4-bit Combinational Circuit Shifter

Arithmetic Logic Shift Unit
• Instead of having individual registers performing the micro operations directly,
computer systems employ a number of storage registers connected to a common
operational unit called an Arithmetic Logic Unit (ALU)
Arithmetic Logic Shift Unit cont.

S3
S2
S1 Ci
S0

One stage of Di
arithmetic
circuit (Fig.A)
Select
One stage of Fi
ALU Ci+1 0 4×1
1 MUX
One stage of Ei 2
logic circuit
Bi (Fig.B) 3
Ai
shr
Ai+1
shl
Ai-1
BASIC COMPUTER ORGANIZATION AND DESIGN
• Instruction Codes

• Computer Registers

• Computer Instructions

• Timing and Control

• Instruction Cycle

• Memory Reference Instructions

• Input-Output and Interrupt

• Complete Computer Description

• Design of Basic Computer

• Design of Accumulator Logic

 INTRODUCTION
• Every different processor type has its own design (different registers,
buses, micro operations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed execution
– Etc.
• However, to understand how processors work, we will start with a
simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls the Basic
Computer
• We will use this to introduce processor organization and the
relationship of the RTL model to the higher level computer processor
 THE BASIC COMPUTER

• The Basic Computer has two components, a processor and memory

• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long

CPU RAM
0

15 0

4095
 INSTRUCTION
S
• Program
– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a specific operation (a
sequence of micro-operation)
• The instructions of a program, along with any needed data are
stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction
into the sequence of microoperations necessary to implement it
 Instruction codes

INSTRUCTION
FORMAT
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that instruction
– An address that specifies the registers and/or locations in memory to use for
that operation
• In the Basic Computer, since the memory contains 4096 (= 212)
words, we needs 12 bit to specify which memory address this
instruction will use
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode

Instruction Format
15 14 12 11 0
I Opcode Address

Addressing
mode
 ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the operand), or
– Indirect address: the address in memory of the address in memory of the data to use

Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand
1350 Operand

+ +
AC AC
 PROCESSOR REGISTERS
• A processor has many registers to hold instructions, addresses, data,
etc
• The processor has a register, the Program Counter (PC) that holds the
memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096 locations, the PC only needs
12 bits
• In a direct or indirect addressing, the processor needs to keep track of
what locations in memory it is addressing: The Address Register (AR)
is used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect addressing,
it is placed in the Data Register (DR). The processor then uses this
value as data for its operation
• The Basic Computer has a single general purpose register – the
Accumulator (AC)
 PROCESSOR REGISTERS
• The significance of a general purpose register is that it can be referred to
in instructions
– e.g. load AC with the contents of a specific memory location; store the contents of AC
into a specified memory location
• Often a processor will need a scratch register to store intermediate
results or other temporary data; in the Basic Computer this is the
Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output (I/O)
operations
– Input devices are considered to send 8 bits of character data to the processor
– The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from an input
device
• The Output Register (OUTR) holds an 8 bit character to be send to an
output device
 BASIC COMPUTER REGISTERS
Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
 Registers

COMMON BUS SYSTEM

• The registers in the Basic Computer are connected using a bus

• This gives a savings in circuitry over complete connections
between registers
 Registers

COMMON BUS SYSTEM

S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2
LD INR CLR

DR 3

LD INR CLR
E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
 Registers

COMMON BUS SYSTEM

Read
INPR
Memory Write
4096 x 16
Address E ALU

AC

L I C

L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus

S0 S 1 S 2
 Registers

COMMON BUS SYSTEM

• Three control lines, S2, S1, and S0 control which register the bus
selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

• Either one of the registers will have its load signal activated, or
the memory will have its write signal activated
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the bus in
the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the data
comes from the low order 8 bits on the bus
 Instructions

BASIC COMPUTER
INSTRUCTIONS
• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation
 Instructions

BASIC COMPUTER
Hex Code INSTRUCTIONS
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
 Instructions

INSTRUCTION SET COMPLETENESS

A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is
known to be computable.
• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT
 Instruction codes

CONTROL
UNIT
• Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations that
implement them

• Control units are implemented in one of two ways

• Hardwired Control
– CU is made up of sequential and combinational circuits to generate the control
signals
• Microprogrammed Control
– A control memory on the processor contains microprograms that activate the
necessary control signals

• We will consider a hardwired implementation of the control unit

for the Basic Computer
 Timing and control

TIMING AND
CONTROL
Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock
 Timing and control

TIMING
SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC
 INSTRUCTION CYCLE

• In Basic Computer, a machine instruction is executed in the

following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect
address
4. Execute the instruction

• After an instruction is executed, the cycle starts again at step 1, for

the next instruction

• Note: Every different processor has its own (different)

instruction cycle
 Instruction Cycle

FETCH and DECODE

• Fetch and Decode T0: AR PC
T1: IR  M [AR], PC  PC + 1
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1
S2
T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus
 Instrction Cycle

DETERMINE THE TYPE OF

INSTRUCTION
Start
SC  0

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D7IT3: Execute an input-output instr.

D7I'T3: Execute a register-reference instr.
D'7IT3: AR M[AR]
D'7I'T3: Nothing
 Instruction Cycle

REGISTER REFERENCE
INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPArB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZErB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
 MR Instructions

MEMORY REFERENCE
Operation
INSTRUCTIONS
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
 MEMORY REFERENCE INSTRUCTIONS
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory
 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
 MR Instructions

FLOWCHART FOR MEMORY REFERENCE

INSTRUCTIONS
Memory-reference instruction

AND ADD LDA STA

D0T 4 D1T 4 D2T 4 D 3T 4

DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0T 5 D1T 5 D2T 5

AC  AC DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4T 4 D5T 4 D6T 4

PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5T 5 D6T 5
PC  AR DR  DR + 1
SC  0
D6T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
 I/O and Interrupt

INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer
• Input-Output Configuration
Input-output Serial Computer
terminal communication registers and
interface
flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
 I/O and Interrupt

PROGRAM CONTROLLED DATA TRANSFER

-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop
INPR  new data, FGI  1
AC  INPR, FGI  0

/* Output */ /* Initially FGO = 1 */ loop: If FGO = 1 goto loop

loop: If FGO = 0 goto loop consume OUTR, FGO  1
OUTR  AC, FGO  0

FGI=0 FGO=1
Start Input Start Output

FGI  0
AC  Data
yes yes
FGI=0
FGO=0
no
no
AC  INPR
OUTR  AC

yes More FGO  0

Character
yes More
no Character
END no
END
 INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off
 I/O and Interrupt

PROGRAM-CONTROLLED
INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware

Input

LOOP, SKI
BUN LOOP
INP

Output
LOOP, LDA DATA
LOP, SKO
BUN LOP
OUT
 INTERRUPT INITIATED INPUT/OUTPUT
- Open communication only when some data has to be passed --> interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions

- when cleared, the computer cannot be interrupted
 I/O and Interrupt

FLOWCHART FOR INTERRUPT

CYCLE R = Interrupt f/f
Instruction cycle =0 =1 Interrupt cycle
R

Fetch and decode Store return address

instructions in location 0
M[0]  PC

Execute =0
IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
=1 IEN  0
FGO R0
=0
R1

- The interrupt cycle is a HW implementation of a branch

and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"
 I/O and Interrupt

REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE

Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0

Register Transfer Statements for Interrupt Cycle

- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R  1

- The fetch and decode phases of the instruction cycle

must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0:AR  0, TR  PC
RT1:M[AR]  TR, PC  0
RT2:PC  PC + 1, IEN  0, R  0, SC  0
 I/O and Interrupt

FURTHER QUESTIONS ON INTERRUPT

How can the CPU recognize the device

requesting an interrupt ?

Since different devices are likely to require

different interrupt service routines, how can
the CPU obtain the starting address of the
appropriate routine in each case ?

Should any device be allowed to interrupt the

CPU while another interrupt is being serviced ?

How can the situation be handled when two or

more interrupt requests occur simultaneously ?
 Description
COMPLETE COMPUTER
DESCRIPTION
Flowchart of Operations
start
SC  0, IEN  0, R  0

=0(Instruction =1(Interrupt
R
Cycle) Cycle)
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) =0(Memory Ref)

D7

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)

I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction
 Description
COMPLETE COMPUTER DESCRIPTION
Microoperations
Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect AR  M[AR]
D7IT3:
Interrupt
T0T1T2(IEN)(FGI + FGO): R1
AR  0, TR  PC
RT0: M[AR]  TR, PC  0
RT1: PC  PC + 1, IEN  0, R  0, SC  0
Memory-Reference RT2:
AND DR  M[AR]
D0T4: AC  AC  DR, SC  0
ADD D0T5: DR  M[AR]
D1T4: AC  AC + DR, E  Cout, SC  0
LDA DR  M[AR]
D1T5:
AC  DR, SC  0
STA D2T4:
M[AR]  AC, SC  0
BUN D2T5: PC  AR, SC  0
BSA D3T4: M[AR]  PC, AR  AR + 1
D4T4: PC  AR, SC  0
ISZ D5T4: DR  M[AR]
D5T5: DR  DR + 1
D6T4: M[AR]  DR, if(DR=0) then (PC  PC + 1),
D6T5: SC  0
D6T6:
 Description
COMPLETE COMPUTER DESCRIPTION
Microoperations

Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA AC  0
rB11:
CLE E0
CMA rB10:
AC  AC
CME rB9: E  E
CIR rB8: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB7: AC  shl AC, AC(0)  E, E  AC(15)
INC rB6: AC  AC + 1
SPA rB5: If(AC(15) =0) then (PC  PC + 1)
SNA rB4: If(AC(15) =1) then (PC  PC + 1)
SZA If(AC = 0) then (PC  PC + 1)
SZE rB3:
If(E=0) then (PC  PC + 1)
HLT rB2: S0
rB1:
Input-Output rB0: (Common to all input-output instructions)
(i = 6,7,8,9,10,11)
D7IT3 = p SC  0
INP IR(i) = Bi AC(0-7)  INPR, FGI  0
OUT p: OUTR  AC(0-7), FGO  0
SKI pB11: If(FGI=1) then (PC  PC + 1)
SKO If(FGO=1) then (PC  PC + 1)
ION pB10:
IEN  1
IOF pB9: IEN  0
pB8:
pB7:
pB6:
 Design of Basic Computer

DESIGN OF BASIC COMPUTER(BC)

Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops:
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC

Control Logic Gates

- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- Adder and Logic circuit
 Design of Basic Computer

CONTROL OF REGISTERS AND MEMORY

Address Register; AR
Scan all of the register transfer statements that change the content of AR:
R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D'7IT3

CLR(AR) = RT0
INR(AR) = D5T4
12 12
From bus AR To bus
D'7
I
LD Clock
T3
T2 INR
CLR
R
T0
D
T4
 Design of Basic Computer

CONTROL OF FLAGS
IEN: Interrupt Enable Flag
pB7: IEN  1 (I/O Instruction)
pB6: IEN  0 (I/O Instruction)
RT2: IEN  0 (Interrupt)

p = D7IT3 (Input/Output Instruction)

D
7
p
I J IEN
Q
B7
T3

B6
K
R
T2
 Design of Basic Computer

CONTROL OF COMMON BUS

x1
x2 S2
Multiplexer
x3
Encoder S1 bus select
x4
x5 inputs
x6 S0
x7

selected
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

For AR D4T4: PC  AR
D5T5: PC  AR

x1 = D4T4 + D5T5
 Design of AC Logic

DESIGN OF ACCUMULATOR LOGIC

Circuits associated with AC 16
Adder and
16 16 16
From DR logic AC

8 circuit To bus
From INPR

LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR
rB9: AC  AC Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left
rB11 :AC  0 Clear
rB5 : AC  AC + 1 Increment
 Design of AC Logic

CONTROL OF AC REGISTER

Gate structures for controlling

the LD, INR, and CLR of AC

From Adder 16 16 To bus

and Logic AC
D0 AND LD Clock
T5 INR
D1 ADD CLR
D2 DR
T5
p INPR
B 11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B 11
 Design of AC Logic

ALU (ADDER AND LOGIC

CIRCUIT)

One stage of Adder and Logic circuit

DR(i)
AC(i)

AND

Ci ADD LD
FA Ii J Q
DR AC(i)
C i+1

INPR K
From
INPR
bit(i)
COM

SHR
AC(i+1)
SHL
AC(i-1)