Lecture 1:

Introduction to Digital Logic Design

CSE 140: Components and Design Techniques for Digital
Systems
Spring 2019

CK Cheng
Dept. of Computer Science and Engineering
University of California, San Diego
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 Outlines
• Class Schedule and Enrollment
• Staff
– Instructor, TAs, Tutors
• Logistics
– Websites, Textbooks, Grading Policy
• Motivation
– Moore’s Law, Internet of Things, Quantum
Computing
• Scope
– Position among courses
– Coverage 2
 Class Schedule and Enrollment
• CSE140 A (enrollment 175, waitlist 19)
– Lecture: TR 5-620PM, PCYNH 106
– Discussion: F 11-1150AM, PCYNH 106
– Final: S 1130AM-130PM, 6/8/2019
• CSE140 B (enrollment 180, waitlist 9)
– Lecture: TR 2-320PM PCYNH 109
– Discussion: F 8-850PM, PCYNH 109
– Final: S 1130AM-130PM, 6/8/2019
• Waitlist: I welcome all students but have no
control of the enrollment
• No discussion session on Friday 4/5/2019
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 Information about the Instructor
• Instructor: CK Cheng
• Education: Ph.D. in EECS UC Berkeley
• Industrial Experiences: Engineer of AMD, Mentor
Graphics, Bellcore; Consultant for technology
companies
• Email: [email protected]
• Office: Room 2130 CSE Building
• Office hours are posted on the course website
– 12-1PM Monday; 10-1050AM Thursday
• Websites
– http://cseweb.ucsd.edu/~kuan
– http://cseweb.ucsd.edu/classes/sp19/cse140-a
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 Information about TAs and Tutors
TAs
• Wang, Ariel Xinyuan email:[email protected]
• Hsu, Po-Ya email:[email protected]
• Assare, Omid email:[email protected]
Tutors
• Lin, Xiaokang, [email protected]
• Liu, Hanshuang [email protected]
• Luo, Weisi [email protected]
• Nichols, Andrew [email protected]
• Ren, Alissa, [email protected]
• Zhang, Shirley, [email protected]
• Zhu, Zhuowen, [email protected]
Office hours will be posted on the course website

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 Logistics: Sites for the Class
• Class website
– http://cseweb.ucsd.edu/classes/sp19/cse140-a/index.html
– Index: Staff Contacts and Office Hrs
– Syllabus
• Grading policy
• Class notes
• Assignment: Homework and zyBook Activities
• Exercises: Solutions and Rubrics
• Forum (Piazza): Online Discussion *make sure you have access
• Score keepers: Gradescope, TritonEd
• zyBook: UCSDCSE140ChengSpring2019

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 Logistics: Textbooks
Required text:
• Online Textbook: Digital Design by F. Vahid
1. Sign in or create an account at learn.zybooks.com
2. Enter zyBook code UCSDCSE140ChengSpring2019
3. Fill email address with domain @ucsd.edu
4. Fill section A or B
5. Click Subscribe $50
Reference texts (recommended and reserved in library)
• Digital Design, F. Vahid, 2010 (2nd Edition).
• Digital Design and Computer Architecture, D.M. Harris and S.L.
Harris, Morgan Kaufmann, 2015 (ARM Edition).
• Digital Systems and Hardware/Firmware Algorithms, Milos D.
Ercegovac and Tomas Lang.
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 Lecture: iCliker for Peer Instruction
• I will pose questions. You will
– Solo vote: Think for yourself and select answer
– Discuss: Analyze problem in teams of three
• Practice analyzing, talking about challenging concepts
• Reach consensus
– Class wide discussion:
• Led by YOU (students) – tell us what you talked about in
discussion that everyone should know.
• Many questions are open, i.e. no exact solutions.
– Emphasis is on reasoning and team discussion
– No solution will be posted
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 Logistics: Grading
Grade on style, completeness and correctness
• zyBook exercises: 10% (due Tuesday 2:00PM)
• iClicker: 0%
• Homework: 15% (grade based on a subset of problems)
• Midterm 1: 25% (T 4/23/19)
• Midterm 2: 25% (T 5/14/19)
• Final: 25% (1130AM-130PM, Saturday 6/8/19)
• Grading: The best of the following
– The threshold: A- >90% ; B- >80% of 100% score
– The curve: (A+,A,A-) top 33±ε% of class; (B+,B,B-) second
33±ε%
– The bottom: C- above 45% of 100% score.

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 Logistic: grading components
• zyBook: Interactive learning experience
– No excuse for delay (constrained by ZyBooks system)
• iClicker:
– Clarification of the concepts and team discussion
• Homework:
• Paper Work
• Group discussion is encouraged. However, we are required
to write individually.
– Discount 10% loss of credit for each day after the deadline
but no credit after the solution is posted.
– Metric: Posted solutions and rubrics, but not grading results

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 Logistic: Midterms and Final
• Midterms: (Another) Indication of how well we have absorbed
the material
– Samples will be posted for more practices.
– Solution and grading policy will be posted after the exam.
– Midterm 2 is not cumulative but requires a good command
of the Midterm 1 content.
• Final:
– Two hours exam.
– Samples will be posted for more practices.
– Final is not cumulative but requires a good command of the
whole class.

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 Logistic: Class Expectation
• Level 1: Definitions (zyBook)
– Basic concepts
– Motivation
• Level 2: Concepts and Methods (Lecture and slides)
– Key ideas
• Level 3: Hands on Practices (Homeworks)
– Exercises
• Level 4: Command of Materials (Samples of exams)
– Review

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 Course Problems…
Cheating
• What is cheating?
– Studying together in groups is not cheating but encouraged
– Turned-in work must be completely your own.
– Copying someone else’s solution on a HW or Exam is
cheating
– Both “giver” and “receiver” are equally culpable

• We will be better off to work on the problem alone during the

exam.
• We have to address the issue once the cheating is reported by
someone (e.g. TA, Tutor, Student, etc.).

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 Motivation
• Microelectronic technologies have revolutionized our
world: cell phones, internet, rapid advances in
medicine, etc.
• The semiconductor industry has grown from $21
billions in 1985, $335 billions in 2015, to $478
billions in 2018.

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 The Digital Revolution
Integrated Circuit: Many digital operations on the same material

Vacuum tubes

Exponential Growth
of Computation

(1.6 x 11.1 mm)

ENIAC Integrated Circuit Moore’s Law

Stored Program
WWII Model 1949 1965 15
 Building complex circuits

Transistor

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 Robert Noyce, 1927 - 1990
• Nicknamed “Mayor of Silicon
Valley”
• Cofounded Fairchild
Semiconductor in 1957
• Cofounded Intel in 1968
• Co-invented the integrated
circuit

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 Gordon Moore
• Cofounded Intel in
1968 with Robert
Noyce.
• Moore’s Law: the
number of transistors
on a computer chip
doubles every 1.5 years
(observed in 1965)

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 Technology Trends: Moore’s Law

• Since 1975, transistor counts have doubled every two years.

• Moore’s law: wider applications: larger market: higher revenue:
more R&D 19
 New Technologies
• New materials and fabrication for devices
– Low power devices
– Three dimensional integrated circuits
– Graphene
• New architecture
– Machine learning, deep learning
• Quantum computing
Understand the principles to explore the future

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 Artificial Intelligence
• Logic and Reasoning
• Boolean Satisfiability
– Product of sum clauses
– Diagnosis
• States and Sequences
– Sequential Machines
– Reachability
– Controllability
One example of the applications and opportunities
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 Scope
The purpose of this course is that we:
• Learn the principles of digital design
• Learn to systematically debug increasingly
complex designs
• Design and build digital systems
• Learn what’s under the hood of an electronic
component
• Prepare for the future technology revolution

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 Position among CSE Courses
Algos: CSE 100, 101

Application (ex: browser)

CSE 131CSE 120 Operating
Compiler System
Software Assembler (Mac OSX)
Instruction Set
Architecture Processor Memory I/O system Architecture
CSE 141
Datapath & Control
Digital Design CSE 140
Circuit Design
Transistors

• Big idea: Coordination of many levels of abstraction

Dan Garcia
 Principle of Abstraction
Application
programs
Software

Operating
device drivers
Systems

CSE 30 Architecture
instructions

focus of this course

registers

CSE 141 Micro- datapaths

architecture controllers

adders
Logic
CSE 140 memories

Digital AND gates

Circuits NOT gates

Analog amplifiers
Circuits filters
Abstraction: Hiding details when
transistors
they are not important Devices
diodes

Physics electrons 24
 Combinational Logic vs Sequential Network
x1 x1
. .
. fi(x) . si fi(x,s)
. .
xn xn
CLK
Sequential Networks
Combinational logic: 1. Memory
yi = fi(x1,..,xn) 2. Time Steps (Clock)
yit = fi (x1t,…,xnt, s1t, …,smt)
sit+1 = gi(x1t,…,xnt, s1t,…,smt)

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 Scope: Overall Picture of CS140
Data Path Subsystem Input Control Subsystem
Memory File Conditions

Pointer
Select
Sequential
Mux
machine

ALU
Control
Memory
Register
CLK: Synchronizing Clock
Conditions
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BSV: Design specification and modular design methodology
 Scope
Subjects Building Blocks Theory
Combinational AND, OR, NOT, Boolean Algebra
Logic XOR
Sequential AND, OR, NOT, Finite State
Network FF Machine
Standard Operators, Arithmetics,
Modules Interconnects, Universal Logic
Memory
System Design Data Paths, Methodologies
Control Paths
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Combinational Logic
Basics

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 What is a combinational circuit?
• No memory
• Realizes one or more functions
• Inputs and outputs can only have two discrete values
• Physical domain (usually, voltages) (Ground 0V, Vdd 1V)
• Mathematical domain : Boolean variables (True, False)

Differentiate between different representations:

• physical circuit
• schematic diagram
• mathematical expressions

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 Binary Digital Logic

• Simplest representation is “1” and “0” (base-2).

• Choose a physical quantity to represent “1” and “0”
– Usually voltage, but not always (e.g. current, resistance,
magnetic polarization, quantum spin, …)
• Use a transistor to make the switch (operating as a digital
instead of analog device)
– Two states – on / off
– Signals can be high voltage (“1”) or low voltage (“0”)

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 Basic CMOS

”on” NMOS PMOS ”on”

when d s
when
g g
gate is gate is
high s d low
https://en.wikipedia.org/wiki/CMOS#/media/File:Cmos_impurity_profile.PNG

Planar technology
• Complementary Metal Oxide Semiconductor
• Invented in the 1960’s, but took over in the 80’s
• “on” means low resistance, ”off” means high
resistance
• Logic “1” and Logic “0” values are arbitrary
FINFET technology

e.g. logic “1” == 1.0 V, logic “0” == 0.0 V By Irene Ringworm, CC BY-SA 3.0,
https://commons.wikimedia.org/w/index.php?curid=3833512

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Transistors as Switches

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 The most basic CMOS gate - inverter

• When “inp” is “1”, then the nmos is on and the pmos is off – output will be ?
• When “inp” is “0”, then the nmos is off and the pmos is on – output will be ?

Truth Table
Schematic Equation
inp out in out
inp out out = in’
0 1
out =in
1 0

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 Basic Gates – (N)AND gate

AND Y = A & B Y = AB
A B Y
0 0 0 A
0 1 0 B
Y
1 0 0
1 1 1
NAND Y = (A & B)’ Y = (AB)’ What kind of gate is this?
a) AND
A B Y b) NAND
0 0 1 c) Inverter
d) None of the above
0 1 1 Bubble
means
1 0 1 Invert

1 1 0

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 Basic Gates – (N)OR gate
OR Y=A+B Y=A|B
A B Y
0 0 0
0 1 1
1 0 1
1 1 1 A

NOR Y = (A + B)’ Y = (A | B)’ Y

A B Y B
0 0 1
0 1 0
1 0 0 Bubble
means
1 1 0 Invert
NOR is universal gate

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 Boolean Algebra
A branch of algebra in which the values of the
variables belong to a set B (e.g. {0, 1}), has two
operations {+, .} that satisfy the following four
sets of laws.
•Associative laws: (a+b)+c= a+(b+c), (a·b)·c =a·(b·c)
•Commutative laws: a+b=b+a, a·b=b·a
•Distributive laws: a+(b·c)=(a+b)·(a+c),
a·(b+c)=a·b+a·c
•Identity laws: a+0=a, a·1=a
•Complement laws: a+a’=1, a·a’=0
(x’: the complement element of x)
<36>
 Duality
• Swap
  (+, and complement all 0’s and 1’s
• If we can prove a statement using laws of
Boolean algebra true, then the duality of the
statement is also true.
Laws and their duals
Associative (a b) c = a (b c) (a b)c = a(bc)
Commutative
Commutative ab = ba a+b
a+b =
= b+a
b+a
Distributive*
Distributive* a(b+c) = ab + ac a+(bc)=(a+b)(a+c)
Identity
Identity a1 = a a+0
a+0 == aa
Compliment aa’ = 0 a + a’ = 1
Compliment a + a’ = 1

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Representations of combinational circuits:
The Schematic

A Y

• What is the simplest combinational circuit that you

know?

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Representations of combinational circuits
Truth Table: Enumeration of all combinations
Example: AND
id A B Y
0 0 0 0
1 0 1 0
2 1 0 0
3 1 1 1
A Y=AB

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 Boolean Algebra
Similar to regular algebra but defined on sets with only
three basic ‘logic’ operations:

1. Intersection: AND (2-input); Operator: ∙ ,&

2. Union: OR (2-input); Operator: + ,|
3. Complement: NOT ( 1-input); Operator: ‘ ,!

“&, |, !” Symbols in BSV

<40>
 Some Def’s

• Complement : variable with a “BAR” over it or ‘ after it

A’
• Literal : variable or its complement
• Implicant: product of literals
ABC
• Implicate: sum of literals
(A+B+C)
Minterm, maxterm (implicant or implicate that includes all the
inputs)
F(A,B,C,D): ABCD, (A+B+C+D)
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 Boolean algebra and switching functions
Two-input AND ( ∙ ) Two-input OR (+ ) One-input NOT
AND A B OR AB Y
(Complement, ’ )
Y
0 0 0 0 0 0 NOT A Y
0 1 0 0 1 1 0 1
1 0 0 1 0 1 1 0
1 1 1 1 1 1
A A
1 A 1
1
A A
0 0 A
0

For an AND gate, For an OR gate,

0 at input blocks the other inputs 1 at input blocks the other inputs
and dominates the output and dominates the output
1 at input passes signal A 0 at input passes signal A
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 Boolean Algebra
iClicker Q: For two Boolean variables X and Y with
X=1, Y=0, what is function F(X,Y)=X+Y?
A.F(X,Y)=0
B.F(X,Y)=1
C.F(X,Y)=2

<43>
 Boolean Algebra
iClicker Q: For two Boolean variables X and Y with
X=1, Y=0, what is function F(X,Y)=X+X+Y?
A.F(X,Y)=0
B.F(X,Y)=1
C.F(X,Y)=2

<44>
 Boolean Algebra
iClicker Q: For two Boolean variables X and Y with
X=1, Y=0, what is function F(X,Y)=X+XY?
A.F(X,Y)=0
B.F(X,Y)=1
C.F(X,Y)=2

<45>
 Boolean Algebra
iClicker Q: For two Boolean variables X and Y with
X=1, Y=0, what is function F(X,Y)=(X+Y)Y?
A.F(X,Y)=0
B.F(X,Y)=1
C.F(X,Y)=2

<46>
 So, what is the point of representing gates as
symbols and Boolean expressions?
• Given the Boolean expression, we can draw the
circuit it represents by cascading gates (and vice
versa)
a ab
b ab + cd
c y=e (ab+cd)
d cd
e

Logic circuit vs. Boolean Algebra Expression

Simplify the Boolean expression: Reduce the complexity of
the circuit 47
 Switching Expression and Logic Diagrams
• Switching Expression –
– Equations - # literals, # variables, # operators
• Literal is a variable or its complement (e.g. a, a’)
• Variables (e.g. x)
• Operator (e.g. +, ·)
– Schematic / Logic Diagram - # of gates, # nets (wires),
# of pins
• Gate (and, or, etc) – can be more than 2 inputs (e.g. 3
input AND gate)
• Net – wire that connects gates
• Pin - input or output of a gate.

48
 Laws and Logic Diagrams

Associativity Laws
(A+B) + C = A + (B+C)

C A
A B
B C

C A
(AB)C = A(BC) A B
B C
 Laws and Logic Diagrams

Distributive Laws
A ∙(B+C) = A ∙ B + A ∙ C

A
A B
B
A
C
C
A+B ∙ C = (A+B) ∙(A+C)
A
A B
B A
C C
 Switching Expression and Logic

a
a·b
b
a·b + c·d
c y=e·(a·b+c·d)
d c·d
e

Schematic Diagram: Boolean Algebra:

5 primary inputs 5 variables
1 primary output 1 expression
4 components (gates) 4 operators
9 signal nets 5 literals
12 pins
 Switching Expression and Logic
a a·b Cost: #gates, #nets, #pins
b a·b + b’·c
b’ y= d’ ·e ·(a·b+b’·c)
c b’·c
d’
e
Schematic Diagram: Switching Expression:
6 primary inputs 5 variables
1 expression
1 primary output
4 operators (3 ANDs, 1 OR)
4 gates (3 ANDs, 1 OR) 6 literals
10 signal nets
11 pins
Nets are wires, Gates ->transistors
Example: f(a, b, c) = ab + a’c + a’b’

# variables
# literals
# gates

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 Which statement is not true in general?

a
a·b
Schematic Diagram: b
a·b + c·d
5 primary inputs c y=e·(a·b+c·d)
d c·d
4 components (gates)
9 signal nets e Boolean Algebra:
12 pins y=e·(a·b+c·d)
5 literals
4 operators
A. #primary inputs = # literals
B. #gates = # operators
C. #nets = #variables + # operators
D. #pins = # literals + 2 * #operators -1
E. All of them
Based on CK Cheng – CSE140 Spr18
 Logic Diagram/Schematics

https://commons.wikimedia.org/wiki/File:74181aluschematic.png

• Logic circuit vs. Boolean Algebra Expression

• Simplify the Boolean expression: Reduce the complexity
of the circuit 55
 Next class
• Designing Combinational circuits

56