Chapter 3

• 8086/8088 CPU architecture & operation

• Programming model, Pins & signals
• Memory segmentation
• Processor bus cycle (Timing diagram),
 Introduction
• Intel 8086 is a 16-bit microprocessor
• 16-bit means:
- Arithmetic logic unit, internal registers, and
instructions are designed to work with 16-bit
binary words.

09/23/2020 2
• 8086 has 16-bit data bus
• It can read/write data to memory and ports
either 16 bits or 8 bits at a time.
• Has a 20-bit address bus, so it can address any
one of 220 or 1,048,576 memory locations.
• Each of 1,048,576 memory address of 8086
represents a byte-wide location.
• 16-bit words is stored in two consecutive
memory locations.
• If the first byte of the word is at even address
then the 8086 can read entire word in one
operation.

09/23/2020 5
• If the first byte of the word is at odd address
then the 8086 reads the first byte with one
bus operation
• And second byte with another bus operation.
• So, if the first byte of 16-bit word is at even
address, the 8086 can read the entire word in
one operation.
 8086 Features
• 16-bit Arithmetic Logic Unit
• 16-bit data bus (8088 has 8-bit data bus)
• Address bus: 220 = 1,048,576

09/23/2020 8
• The address refers to a byte in memory
• In the 8088, these bytes come in on the 8-bit
data bus.
• In 8086, bytes at even addresses come in on
the low half of the data bus (bits 0-7)
• Bytes at odd addresses come in on the upper
half of the data bus (bits 8-15).
• 8086 can read a 16-bit word at an even
address in one operation
• An odd address in two operations
• 8088 needs two operations in either case.

09/23/2020 11
 8086 Pin Description

09/23/2020 12
 Pin Description

• Two modes of operations:

– Minimum mode &
– Maximum mode
• In microcomputer system, where only one
8086 microprocessor works as CPU, it
operates in the minimum mode.

09/23/2020 13
• But in multiprocessor system, the 8086 works
in maximum mode.
• The status of the pin MN/MX decides the
operation mode of 8086
• When the signal in this pin goes high, 8086
operates in minimum mode
• When the signal goes low, it operates in
maximum mode.
• Pins 24 to 31 of 8086 have alternate functions
• Signals in the bracket are activated in
maximum mode of operation.
• AD15 – AD0 (Bidirectional):
- Time-multiplexed address/data bus
• During T1 clock cycle, it carries lower order
16-bits of address and during T2, T3 and T4, it
carries 16-bit data

09/23/2020 17
• A19/S6 – A16/S3:
- Time-multiplexed lines
• During T1, they carry high order 4 bits of
memory address
• During T2, T3 and T4, these lines carries status
signals.
• The status signals S3 – S6  
- Encoding of S3 and S4
S4 S3 Segment register employed
0 0 ES
0 1 SS
1 0 CS or none
1 1 DS

09/23/2020 19
• S5 and S6
- S5 status signal is the interrupt enable flag bit
- Status bit S6 is always at logic level zero.
BHE/S7: (Bus/Bank High Enable)
• 20-bit address bus and each address can store
8-bits of data.
• When the instruction MOV [215AH], BX is
executed, the word (2 bytes) is actually
written into two consecutive memory
location.

09/23/2020 21
• Assuming DS starts from 0000H, the low byte
of word (i.e. BL) is written into address
0215AH and high byte of the word (i.e. BH) is
written into next higher address 0215BH.
• Normally, it will take 2 machine cycles, as it
needs to write the data two times (higher byte
and lower byte) in memory.
• So to make it possible to read or write a word
in one machine cycle, the memory for 8086 is
set up as two “banks” of up to 524,288 bytes
each.
• One memory bank contains all the bytes
having even addresses such as 00000H,
00002H, 00004H up to FFFFEH.
• The data lines of this memory bank are
connected to the lower eight data line D0 – D7
of 8086.

09/23/2020 25
• The other memory bank contains all the bytes
which have odd addresses such as 00001H,
00003H, 00005H up to FFFFFH.
• The data lines of this memory bank are
connected to the higher eight data line D8 –
D15 of 8086.
09/23/2020 27
• Address line A0 is used to enable the memory
device in the lower bank.
• When A0 become low, it selects the lower
bank memory device as it indicates the even
address.

09/23/2020 28
• Address line A1 through A19 are used to select
the desired memory location in upper and
lower bank of memory.
• Similarly, BHE (Bus/Bank High Enable) signal is
used to enable the upper memory bank
• BHE in conjunction with A0 determines
whether a byte or words will be transferred
from/to memory location
BHE A0 Word/Byte Access
0 0 Whole word (from/to both upper and lower
bank)
0 1 Upper byte from/to odd address
1 0 Lower byte from/to even address
1 1 None (Both memory will be unselected)

09/23/2020 31
• During T2 to T4, the status line S7 is
transmitted and it remains always high.
• NMI: Non Maskable Interrupt Request
•  INTR: Interrupt Request
• CLK: Clock for 8086
•  RESET
- System reset and an active high signal
- When it goes high the microprocessor goes into
reset state.

09/23/2020 33
• READY
- Acknowledgement received from the
addressed memory or I/O device.
- It is an active high signal
- When it goes high, the peripheral (memory
device) is ready to receive or transfer a data.
• TEST
- Test the status of the MP
- When TEST signal become low, the 8086 goes
to the next instruction.
• INTA (Interrupt Acknowledge)
- On receiving interrupt request signal, MP
issues an interrupt acknowledge signal
•  ALE
- Used to latch the address into the address latch
(8282/8283).

09/23/2020 36
• MN/MX
- Indicates operating mode
- When the signal goes high, the processor
operates in the minimum mode.
- When low, it operates in the maximum mode.
• RD
- Read signal issued by the MP
- Active low signal
- It indicates that the MP is performing read
operation.
• HOLD
- It goes high when the external devices want to
take control of address and data buses.
• HLDA (Hold Acknowledge)
- MP sends high signal to acknowledge that it
has received a ‘HOLD’ request
- Release the control of buses in next cycle.

09/23/2020 39
• WR
- When this signal goes low, the processor
performs memory or I/O write operations.
•  M/IO
- Distinguish a memory access from I/O access
- When goes high MP accesses memory
- When goes low MP accesses I/O devices.

09/23/2020 40
• DT/R (Data transmit and receive)
- When the minimum mode system
incorporates this signal is required for data
flow control.
- When it is high data are sent out
- When it goes low, data are received by MP

09/23/2020 41
• DEN (Data Enable)
- Active low signal
- In the minimum mode of operation, this signal
is issued by the MP
 8086 Internal Architecture

• Two separate (independent) units:

– Bus Interface Unit (BIU)
– Execution Unit (EU)
• These units are used to speed up processing.

09/23/2020 43
• BIU fetches instructions, reads and writes
data, and computes the 20-bit address.
• EU decodes and executes the instructions
using the 16-bit ALU.
8086 [Internal Architecture] Block Diagram

09/23/2020 45
 Bus Interface Unit (BIU)

• Sends out addresses

• Fetches instruction from memory
• Reads data from memory and I/O ports
• Writes data to memory & I/O ports

09/23/2020 46
• Transfer of data and addresses on the buses
for the execution unit.
• Interface of execution unit
BIU is divided into the following sub units:
– Instruction Queue
– Instruction Pointer
– Segment Register
– Bus Control and Address Generator

09/23/2020 48
 Instruction Queue

• First-In-First-Out (FIFO) group registers

• Up to 6 bytes of instruction are pre-fetched
from memory.
• This is done in order to speed up execution of
program

09/23/2020 49
• Fetching the next instruction while the current
instruction executes is called Pipelining.
• When the EU is decoding an instruction the
BIU fetches up to six instruction bytes
• BIU stores these pre-fetched bytes in a FIFO
out register set called queue.
 Instruction Pointer (IP)

• Points to the next instruction to be fetched

from memory.
• 16-bit
• The value contained in IP is referred as an
offset

09/23/2020 52
 Segment Registers

• 8086 BIU sends out 20-bit addresses, so it can

address any of 220 or 1,048,576 bytes
• 8086 works with only four 64-Kbytes (65,536
bytes) segments

09/23/2020 53
• Four segment registers are used to hold the
upper 16 bits of the starting addresses of four
memory segments.
 The BIU contains the following segment
registers:
• CS - the Code Segment Register
• DS - the Data Segment Register
• SS - the Stack Segment Register
• ES - the Extra Segment Register
• And Instruction Pointer(IP)

09/23/2020 55
 Stack Segment Register

• Stack: store addresses and data while a

subprogram is executing.
• 8086 allows to set aside an entire 64-Kbyte
segment as a stack.
• Upper 16 bits of the address for this segment
are kept in the stack segment register.

09/23/2020 56
• Stack Pointer (SP) in EU holds the 16-bit offset
from the start of the segment to the memory.
• Memory location where a word was most
recently stored is called the top of stack.
 Others Segment Registers

• 16-bit base pointer (BP) register

• 16-bit source index (SI) register
• 16-bit destination index (DI) register.
• Used for the temporary storage of data
• Hold the 16-bit offset of a data word in one of the
segments.

09/23/2020 58
• SI can be used to hold the offset of the data
word in a data segment.
• The physical address of the data in memory
gets generated by adding the contents of SI to
the segment base address in the DS register.
• The BIU fetches instructions using the CS and
IP
• 20-bit address.
• Data is fetched using a segment register

09/23/2020 60
 Execution Unit (EU)

• Fetches instructions or data

• Decodes and executes instructions.
• Handles all controlling functions.

09/23/2020 61
• BIU and EU are designed to work
simultaneously.
• As a result processing time required for an
instruction will be reduced.
• EU contains control circuitry which directs
internal operations.
• A decoder in the EU translates instructions
fetched from memory
• Has a 16-bit ALU

09/23/2020 63
 ES Extra Segment
BIU registers CS Code Segment
(20 bit adder) SS Stack Segment
DS Data Segment
IP Instruction Pointer

EU registers
AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS

09/23/2020 64
 General Purpose Registers

• EU has eight general purpose registers,

labeled AH, AL, BH, BL,CH,CL, DH and DL.
• Used for temporary storage of 8-bit data.
• The AL register is also called as Accumulator.

09/23/2020 65
• Certain pairs of these registers can be used
together to store 16-bit data words.
• The acceptable register pairs are:
-AH and AL, BH and BL, CH and CL and DH and
DL
• AH and AL = AX etc.
• The EU contains the following 16-bit registers:
» AX - the Accumulator
» BX - the Base Register
» CX - the Count Register
» DX - the Data Register
» SP - the Stack Pointer \ defaults to stack segment
» BP - the Base Pointer /
» SI - the Source Index Register
» DI - the Destination Register

09/23/2020 67
• The AX, BX, CX, and DX registers can be
considers as two 8-bit registers
• High byte and a Low byte
• Byte operations and compatibility

09/23/2020 68
• The 8-bit registers are:
»AX --> AH,AL
»BX --> BH,BL
»CX --> CH,CL
»DX --> DH,DL
 Flag Register in EU

• Execution of an instruction or
• Controls certain operations of the EU.
• A 16-bit flag register in EU contains nine active
flags.

09/23/2020 70