ECE - 1551

DIGITAL LOGIC
LECTURE 15: COMBINATIONAL CIRCUITS

Assistant Prof. Fareena Saqib

Florida Institute of Technology
Fall 2015, 10/20/2015
Recap

 Design Modeling using VHDL

 DataFlow Modeling
 Structural Modeling
 Behavioral Modeling.

 Introduction to Arithmetic Circuits.

 Half Adder
 Full Adder
Binary Adder

 A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers of more than 1 bit, f.g.
addition of 2 four bit numbers.

 A simple binary adder (Full Adder) is shown in the figure below.

 Binary adder can be constructed by cascading full adders, with the output carry from each full adder connected to the
input of next full adder in the chain.
 Thus the addition on n-bit numbers requires a chain of n full adders.
 Or a chain of one half adder and n-1 full adders.
Binary Ripple Carry Adder

 The interconnection of four full adders circuits in a chain creates a four-bit Binary Ripple Carry Adder.

 The augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with
subscript 0 denoting the least significant.

 The S outputs generate the required sum, and the carries are connected in a chain trough the full adders.
The input carry to the adder is C0, and it ripples trough the full adders to the output carry C4.
Binary Ripple Carry Adder contd.

 To demonstrate with a specific example, consider the two binary numbers A = 1011and B = 0011. Their
sum S = 1110 is formed with the four-bit adder as follows:

 The bits are added with full adders, starting from the least significant position (subscript 0), to form the
sum bit and carry bit.

 It is important to note that the design of this circuit by the classical method would require a truth table
with 2^9 = 512 entries, since there are nine inputs to the circuit.
Carry Propagation

 The addition of two binary numbers in parallel implies that all the bits of the augend and the addend are
available for computation at the same time.

 The total propagation time is equal to the propagation delay of a typical gate, time the number of gate
levels in the circuit. The longest propagation delay time in an adder is the time it takes the carry to
propagate trough the full adders.

 The carry propagation time is an important attribute of the adder because it limits the speed with which
two numbers are added.

 One solution for reducing the carry propagation delay time is to employ faster gates with reduced delays.
However, physical circuits have a limit to their capability.

 Another solution is to increase the complexity of the circuit in such a way that the carry delay time is
reduced.

 There are several techniques for reducing the carry propagation time in a parallel adder. The most widely
used is called a Carry Lookahead Logic.
Carry Propagation

 If we define two new binary variables G and P. (Carry Generate and Carry
Propagate)

 the output sum and carry can respectively be expressed as

 Carry Propagation
Boolean functions for the carry outputs of each stage and substitute the value of each Ci from the
previous equations:
Carry Lookahead Adder

Logic Diagram of Carry Lookahead Generator Four-bit adder with carry lookahead
Binary Subtraction

 Binary subtraction using complements.

 subtraction A - B can be done by taking the 2’s complement of B and adding it to
A.
 The 2’s complement can be obtained by taking the 1’s complement and adding 1 to
the least significant pair of bits.
 The 1’s complement can be implemented with inverters, and a 1 can be added to
the sum through the input carry.
Overflow for Signed and Unsigned numbers

 The detection of an overflow after the addition of two binary numbers depends on whether the numbers
are considered to be signed or unsigned.

 In the case of signed numbers, two details are important: the leftmost bit always represents the sign and
negative numbers are in 2’s complement form.

 When two signed numbers are added, the sign bit is treated as part of the number and the end carry does
not indicate an overflow.

 To see how this can happen, consider the following example: Two signed binary numbers, +70 and +80,
are stored in two eight-bit registers. The range of numbers that each register can accommodate is from
binary +127 to binary -128. Since the sum of the two numbers is +150, it exceeds the capacity of an eight-
bit register. This is also true for -70 and -80. The two additions in binary are shown next, together with the
last two carries:
Overflow contd.

 An Overflow condition can be detected by observing the carry into the sign bit position and the carry put
of the sign bit position. If these two carries are not equal, an overflow has occurred.

 If the two binary numbers are considered to be unsinged, then the C bit detects a carry after addition or a
borrow after subtraction. If the numbers are considered to be signed, the V bit detects an overflow.

Four-bit adder – subtractor with overflow detection

Decimal Adder

 For binary addition, it is sufficient to consider a pair of significant bit together with a previous
carry.
 A decimal adder requires a minimum of nine inputs and five outputs, since four bit are required
to code each decimal digit and the circuit must have an input and output carry.
 There is a wide variety of possible decimal adder circuits, depending upon the code used to
represent the decimal digits.
 We will cover a decimal adder for the BCD code.
BCD Adder

 Consider the arithmetic addition of two decimal digits in BCD together with an input carry
from a previous stage.
 Since each input digit does not exceed 9, the output sum cannot be greater than: 9 + 9 + 1 =
19. The 1 being an input carry.
 Suppose we apply two BCD digits to a four-bit binary adder. The adder will form the sum in
binary and produce a result that ranges from 0 through 19. These binary numbers are listed and
are labeled by symbols K, Z8, Z4, Z2, and Z1. K is the carry, and the subscripts under the letter Z
represent the weights 8, 4, 2, and 1. The columns under the binary sum list the binary value
that appears in the outputs of the four-bit binary adder. The output sum of two decimal digits
must be represented in BCD and should appear in the form listed in the columns under “BCD
Sum.” The problem is to find a rule by which the binary sum is converted to the correct BCD
digit representation of the number in the BCD sum.
BCD Adder

 Looking at the table, it becomes apparent that

when the binary sum is equal to or less than 1001,
the corresponding BCD number is identical, and
therefore no conversion is needed.

 When the binary sum is greater than 1001, we

obtain an invalid BCD representation. The
addition of binary 6 (0110) to the binary sum
coverts it to the correct BCD representation and
also produces an output carry as required.
BCD Adder

 It is obvious that a correction is needed when the

binary sum has an output carry K = 1.

 The other six combinations from 1010 through

1111 that need a correction have a 1 in position Z8.
To distinguish them from binary 1000 and 1001,
which also have a 1 in position Z8, we specify
further that either Z4 or Z2 must have a 1. The
Boolean function for the correction can be
expressed as: C = K + Z8Z4 + Z8Z2. When C = 1, it
is necessary to add 0110 to the binary sum and
provide an output carry for the next stage.
BCD Adder

 A BCD adder that adds two BCD digits and

produces a sum digit in BCD is shown in the
figure below.

 The two digits, together with the input carry, are

first added in the top four-bit adder to produce
the binary sum. When the output carry is equal
to 0, nothing is added to the binary sum.

 When it is equal to 1, binary 0110 is added to

the binary sum through the bottom four-bit
adder.

 The output carry generated from the bottom

adder an be ignored, since is supplies
information already available at the output carry
terminal.
 Binary Multiplier

 Multiplication of binary numbers is performed

in the same way as multiplication of decimal
numbers.
 consider the multiplication of two 2-bit
numbers.
Multiplier
Multiplicand

1 two bit adder

 For J multiplier bits and K multiplicand bits, we

need (J * K) AND gates and (J – 1) K -bit
adders to produce a product of (J + K) bits.
Four bit by three bit

 Example:
 Consider a multiplier circuit that
multiplies a binary number represented
by four bits by a number represented by
three bits.
 Multiplicand be represented by B3B2B1B0
and
 Multiplier by A2A1A0.

 We need two Adders each of four bits