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Test Bench For 8 Bit Counter

This document contains a test bench for a 8-bit counter component written in VHDL. The test bench defines the component interface, instantiates the component, and generates a clock signal to test the component behavior over time.

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Anuradha Khalkho
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© © All Rights Reserved
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81 views

Test Bench For 8 Bit Counter

This document contains a test bench for a 8-bit counter component written in VHDL. The test bench defines the component interface, instantiates the component, and generates a clock signal to test the component behavior over time.

Uploaded by

Anuradha Khalkho
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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vhdl code
• Test bench:
• LIBRARY ieee;
• USE ieee.std_logic_1164.ALL;
•  
•
• ENTITY Bitcounter_8_tb IS
• END Bitcounter_8_tb;
•
• ARCHITECTURE behavior OF Bitcounter_8_tb IS
•
• -- Component Declaration for the Unit Under Test (UUT)
•
• COMPONENT Bitcounter_8
• PORT(
• CLK : IN std_logic;
• OUTPUT : OUT std_logic_vector(7 downto 0)
• );
• END COMPONENT;
•
•  
• --Inputs
• signal CLK : std_logic := '0';
•  
• --Outputs
• signal OUTPUT : std_logic_vector(7 downto 0);
•  
• -- Clock period definitions
• constant CLK_period : time := 10 ns;
•
• BEGIN
•
• -- Instantiate the Unit Under Test (UUT)
• uut: Bitcounter_8 PORT MAP (
• CLK => CLK,
• OUTPUT => OUTPUT
• );
•  
• -- Clock process definitions
• CLK_process :process
• begin
• CLK <= '0';
• wait for CLK_period/2;
• CLK <= '1';
• wait for CLK_period/2;
• end process;

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