Scribd
Upload
27 views33 pages

WINSEM2017-18 - ECE5023 - TH - TT531A - VL2017185001741 - Reference Material I - Copy of Lecture 2&3

Here are two layouts of a 6T SRAM cell with their b factors: Layout 1 (b=1.8): The transistors are laid out in a bar structure. This layout is more susceptible to bridging faults between diffusion regions. The b factor is 1.8. Layout 2 (b=2.1): The transistors are laid out in an H-shape with the pull-up PMOS transistors on the outside. This layout takes more area but the transistors are farther apart reducing bridging faults. The b factor is higher at 2.1.

Uploaded by

Aashish
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
27 views33 pages

WINSEM2017-18 - ECE5023 - TH - TT531A - VL2017185001741 - Reference Material I - Copy of Lecture 2&3

Here are two layouts of a 6T SRAM cell with their b factors: Layout 1 (b=1.8): The transistors are laid out in a bar structure. This layout is more susceptible to bridging faults between diffusion regions. The b factor is 1.8. Layout 2 (b=2.1): The transistors are laid out in an H-shape with the pull-up PMOS transistors on the outside. This layout takes more area but the transistors are farther apart reducing bridging faults. The b factor is higher at 2.1.

Uploaded by

Aashish
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 33

Lecture 2

Read:
Chapter 1 of Text: Dean Adams

Detailed Tech. Intro. in Chapter 1 of Text: A. K. Sharma


Memory Block Diagram

Data Inputs

Write Drivers
Address Inputs

Decoders

Memory Array

Sense Amplifier

Data Outputs
Semiconductor Memory Types

Volatile Non-Volatile Read-Only Memory


Read-Write Memory Read Write
Memory

Random Access Non-Random EPROM Mask Programmed (ROM)


Access EEPROM
(E2PROM) Programmable ROM (PROM)
FLASH

FIFO
SRAM LIFO
DRAM Shift Register
CAM
Introduction to SRAM
SRAM’s
• Past, present and future workhorses of memories

• First memories were SRAM’s

• # of embedded SRAM’s > DRAM’s

• Are the fastest. Used e.g. in L1 caches of mP

• Low power

• No data refresh needed

• Easiest to use(Interface)
SRAM Trends
SRAM Cell Structure
• SRAM cell must be:
1. easy to write
2. stable, both in a quiescent state and when being read
• Early NMOS – 4 enhancement mode + 2 depletion mode

• R-load NMOS – ion-implanted Poly Si load resistors for pull-


up, improvement in cost and power

• Mixed MOS/R-load CMOS- NMOS transistor matrix with high


W loads and CMOS peripheral Ckts. – low standby power and
area- leakage currents in the range of mA

• Full CMOS – leakage currents in the range of nA.


structures….contd
MOS SRAM Architecture
Architecture …..contd

• The square array


occupies the least area

• Rectangular arrays can


also be made
MOS SRAM Cell and Peripheral Circuit Operation

1. Read Operation

• To read data, set the corresponding bit and bit-bar lines HIGH then
raise the required word line

• If a data 1 is stored the o/p of the Diff. Amp. Connected to bit and bit-
bar line is positive

• If a data 0 is stored the o/p of the Diff. Amp. Is negative

• Read-out is non-destructive
2. Write Operation

• To write data 1 onto a cell –select the word line and then drive the
corresponding bit and bit-bar lines high and low respectively

• To write data 0 onto a cell –select the word line and then drive the
corresponding bit and bit-bar lines low and high respectively
Peripheral Circuitry
• Read Data Path
Pre-charge circuitry

Isolation circuitry

Sense amplifier

Refer : Dean Adams


Precharge circuit
Isolation circuit
Sense Amplifier
…contd
• Write Driver Circuitry
…contd
• Decoder circuitry
Static or Dynamic

Static
Layout considerations
• Cell stepping, mirroring, rotating
• Bit line twisting
Redundancy

Extra memory to replace defective


memory

Spare rows, I/O, columns, blocks, or a


combination
Peripheral ….contd
SRAM Parameters

• Read Access Time: is the propagation delay from the time


the address is presented at the memory chip until the data are
available at the memory o/p

• Cycle Time: is the minimum time that must be allowed after the
initiation of the R/W operation before another operation can be
initiated
Parameters...contd

• The Cell stability parameter, b ratio, defined as the ratio of the


strength of the pull-down transistor to the strength of the transfer
transistor

( weff ) pull down /(leff ) pull down



( weff ) transfer /(leff ) transfer

b ratio of 1.5-2.0 is typical in the industry

If b < 1.0 then the cell readout is destructive


The Butterfly curve

• A large square box means a stable cell


Layout considerations

• Different layout styles are sensitive to different manufacturing


defects and fail differently

• Therefore different Fault Models and Testing Patterns should be


used for different designs
Layouts….contd
Layouts….contd
Exercise 1

• Make two different layouts of a 6-T SRAM cell.


Determine the b factor of each and discuss how the
layouts are susceptible to faults

You might also like