EE3101 Communication Engineering: Chapter 3-1, Synchronization
EE3101 Communication Engineering: Chapter 3-1, Synchronization
Communication Engineering
Chapter 3-1, Synchronization
Course Intended Learning Outcomes
Describe the importance of synchronization
3.1 Introduction
Basic techniques for carrier and symbol synchronization
3.2 Phase Locked Loop (PLL)
3.3 Carrier Synchronization
3.4 Symbol Synchronization
3.1 Introduction
(1) Consider a BPSK receiver; there exists a phase offset (t), or a frequency offset
Due to locally generated carrier frequency. Assuming that the symbol rate is much
slower than the carrier;
𝑇
2
0 𝑇 √
𝑧 ( 𝑇 )=∫ 𝑟 (𝑡) 𝑐𝑜𝑠 [ 𝜔 𝑐 𝑡 +𝜃(𝑡) ] 𝑑𝑡
𝑇
( ∗ ) 𝑑𝑡 𝑧 (𝑇 ) Decision
𝑟 ( 𝑡 ) ∫ stage
0
1
2 𝑧 (𝑇 ) ≷ 0
√ 𝑇
𝑐𝑜𝑠 ( 𝜔 𝑐 𝑡 ) 0
For binary “1”
Similarly
for binary “0” Example
Z(T)
“1” “0”
0 0
-E E
(2) There also exists a timing offset toffset at the receiver correlator
𝑇 +𝑡 𝑜𝑓𝑓𝑠𝑒𝑡
2
𝑧 ( 𝑇 )= ∫
𝑡 𝑜𝑓𝑓𝑠𝑒𝑡 √
𝑟(𝑡) 𝑐𝑜𝑠 ( 𝜔 𝑐 𝑡 ) 𝑑𝑡
𝑇
If t=T/2 and the received binary data is;
offset
Binary “1” for t=0 to T,
Binary “0” for t=T to 2T,
(3) However accurate the hardware is there exists a tolerance,
Bit rate of transmitter: 99.9999Mb/s
Bit clock of receiver: 100.0005MHz
Without appropriate synchronization, there will exist errors which gets worse with time.
1. Phase Detector
Measures the phase difference of the two
inputs. (example: exclusive OR gate)
𝑟 ( 𝑡 ) 2. Loop Filter
𝑒 (𝑡) Determines the loop response, tracks the
𝑥 (𝑡 )
signal phase but not overly responsive to
received noise.
𝑦 (𝑡) 3. Voltage Controlled Oscillator
𝑉𝐶𝑂
Gives an output frequency as a (linear)
o/p
function of an input control frequency.
Where (t) is a slow varying phase compared to wc.
Note
Loop
Time domain Phase change of
parameters
phase error input signal in
at equilibrium frequency domain
Example 1
Response of a Phase Step;
( 𝑗 𝜔 )2 ∆𝜃 0
lim 𝑒 ( 𝑡 )= lim × = ∆ 𝜃=0 , 𝑖𝑓 𝐹 ( 0 ) ≠ 0
𝑡→∞ 𝑗 𝜔→ 0 𝑗 𝜔 + 𝐾 0 𝐹 ( 𝜔 ) 𝑗 𝜔 0+ 𝐾 𝑜 𝐹 (0)
Example 2
Response of a Frequency Step;
𝑑 𝜃(𝑡 )
𝑁𝑜𝑡𝑒 : 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑐h𝑎𝑛𝑔𝑒= =∆ 𝜔
𝑑𝑡
( 𝑗 𝜔 )2 ∆𝜔 ∆𝜔
lim 𝑒 ( 𝑡 )= lim × 2
=
𝑡→∞ 𝑗 𝜔→ 0 𝑗 𝜔 + 𝐾 0 𝐹 ( 𝜔 ) ( 𝑗𝜔) 𝐾 𝑜 𝐹(0)
F(0)constant; all pass filter or first order low pass filter,
The loop will track the frequency step
F(0)pole at origin; like an integrator,
The loop will eventually track out the error. (0) ∆ 𝜔
lim 𝑒 ( 𝑡 )= =0
𝑡→∞ 𝐾 0 𝐷(0)
Example 3
Response of a Frequency Ramp;
𝑁𝑜𝑡𝑒 : 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦=𝜔 𝑐 + ∆ 𝜔
˙ 𝑡 𝑓𝑜𝑟 𝑡 ≥ 0
( 𝑗 𝜔 )2 ∆ 𝜔˙ ∆𝜔 ˙
lim 𝑒 ( 𝑡 )= lim × 3
= lim
𝑡→∞ 𝑗 𝜔→ 0 𝑗 𝜔 + 𝐾 0 𝐹 ( 𝜔 ) ( 𝑗 𝜔 ) 𝑗 𝜔→ 0 𝑗 𝜔 𝐾 0 𝐹 (0)
F ( 0 ) ⇒ 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 ; 𝑡h𝑒 𝑃𝐿𝐿 𝑐𝑎𝑛𝑛𝑜𝑡 𝑡𝑟𝑎𝑐𝑘 𝑡h𝑖𝑠 𝑠𝑖𝑔𝑛𝑎𝑙 𝑎𝑠 ; lim 𝑒 (𝑡 ) → ∞
𝑗 𝜔→ 0
𝐷(𝜔 )
A t least one pole is required ,example usig single pole ; 𝐹 ( 𝜔 )=
𝑗𝜔
∆𝜔 ˙
T he PLLis able ¿ track but wi 𝑡h 𝑎 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝑝h𝑎𝑠𝑒 𝑒𝑟𝑟𝑜𝑟 ; lim 𝑒 (𝑡)=
𝑗 𝜔 →∞ 𝐾 0 𝐷 (0)
3.2.2 Practical Implementations
• Majority of PLL are second order because
they can be made unconditionally stable.
• Higher order loops are conditionally stable.
𝑟 ( 𝑡 )
𝑒 (𝑡)
• Narrow loop bandwidth H(w) gives smaller
phase variance of VCO output frequency. 𝑥 (𝑡 )
• Narrow loop bandwidth gives poorer tracking
𝑦 (𝑡)
ability.
𝑉𝐶𝑂
• Loop bandwidth should be wider than the
Doppler frequency shift.