Scribd
Upload
295 views

Design and Modeling of I2C Controller

This document describes the design and modeling of an I2C controller. It discusses the objectives of reducing the number of inputs and creating communication between a master and slave device. It provides details on the master's three modes of operation and includes a block diagram of the I2C controller showing its main components. The approach involves generating start and stop bits, obtaining the slave address and data from the user, transmitting the address and data, and waiting for acknowledgment from the slave. It notes the project's current progress in obtaining user inputs and storing them in registers, and creating a test bench for partial output verification.

Uploaded by

Ankit Pachouri
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
295 views

Design and Modeling of I2C Controller

This document describes the design and modeling of an I2C controller. It discusses the objectives of reducing the number of inputs and creating communication between a master and slave device. It provides details on the master's three modes of operation and includes a block diagram of the I2C controller showing its main components. The approach involves generating start and stop bits, obtaining the slave address and data from the user, transmitting the address and data, and waiting for acknowledgment from the slave. It notes the project's current progress in obtaining user inputs and storing them in registers, and creating a test bench for partial output verification.

Uploaded by

Ankit Pachouri
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 18

Design and Modelling of I2C

Controller

Group members:
Prajual P 20MVD1077
Shubhada Budhe 20MVD1078
Shobhit Srivastava 20MVD1079
Ankit Pachouri 20MVD1080
INTRODUCTION
• The interconnect integrated circuit bus commonly known as the I2C
bus which is a bidirectional two wire and serial communication
standard protocol.

• It is designed primarily for simple but efficient integrated circuit


(IC) control. The system is comprised of two bus lines SCL (serial
clock) and SDA (serial data) that carry information between the IC’s
connected to them. .

• Master - The device which generates clock signals, initiates a


transfer i.e start condition and terminates a transfer i.e stop
condition. It may also act as a trasnmitter/receiver.
OBJECTIVE
• Reducing number of inputs

• To create a communication between master and slave.


MASTER
• Three modes of operations
1. Master transmitter mode
2. Master receiver mode
3. Master transmitter followed by repeated START and
becoming master receiver
BASE PAPER
BLOCK DIAGRAM
I2C CONTROLLER
SDA
DATA [7:0] I2C START &STOP BLOCK

DATA_REG
RORW
REG_ADDRESS_REG
SELECTION
BIT [1:0] I2C_ADDRESS SCL
_REG

CLOCK
APPROACH
START BIT:
• Start bit can be generated by changing SDA from high to low
when SCL is high.
APPROACH CONTD.
SLAVE ADDRESS:

• Slave Address is to be obtained from User as input.

• Whether Read or Write Action is to be performed is also


obtained from user input.

• Obtained input slave address is left shifted by 1 and R/W input


is appended. This entirely now forms the Final Slave Address.
APPROACH CONTD.
SLAVE ADDRESS:
• Once Slave Address is transmitted, it waits for
acknowledgment from slave.
• If the SDA line is made low by slave in next clock
pulse then it has acknowledged.
• If the SDA line is pulled up in next clock pulse then
the slave address is not acknowleged.
APPROACH CONTD.
REGISTER ADDRESS/DATA:
• REGISTER ADDRESS/DATA is to be obtained from User as
input.
• Upon Transmitting the data, the same acknowledgment
procedure is to be followed.
APPROACH CONTD.
STOP BIT:
• Stop bit can be generated by changing SDA from low to high
when SCL is high.
PROGRESS
• Obtaining the following inputs from User
– RORW
– Data
– 2bit Selection line
• 00 : I2C_ADDRESS
• 01 : REG_ADDRESS
• 10 : INPUTDATA
• 11 : START_I2C
• Storing the inputs in respective registers.
• Master Transmit Mode Partial Output.
• Creation of Test Bench.
CODE
CODE
TESTBENCH
TEST BENCH PARTIAL OUTPUT
REFERENCES
• Understanding the I2C bus by Texas instruments.

• BOYA NARESH1 , P. VIJAY LAKSHMI2 , T. MAHESHWAR3 , DIWAKAR


TIWARYDesign and implementation of I2C bus controller using Verilog-
2016
Thank you

You might also like