6.

3 Combinational PLDs
PLDs----Programmable Logic Devices
6.3.1 Programmable Logic Arrays
 The first PLDs were PLAs. A PLA is simply a
combinational, two-level AND-OR device that can
be programmed to realize any sum-of-products
logic expression, subject to the size limitations of
the device.
 Limitations are
- the number of inputs (n),
- the number of outputs (m),
- the number of product terms (p).
Programmable Logic Array
Structure

PLA

n Input AND OR

••••••
•••

Lines Array Array

••••••

K Word
m Output Lines
Lines
Internal Structure of a PLA
Inputs
A B C

OR ARRAY
A’ B’ C’
A’B’

AC’

BC’

AC

AND ARRAY
F0 F1 F2 F3
F0=A’B’+AC’
…… Outputs
 Internal Structure of a PLA
Inputs
a b c d

a’ b’ c’ d’
a’bd
abd
ab’c’
b’c
c
bc

F1=a’bd+abd+ab’c’+b’c F1 F2 F3
F2=a’bd+c
Outputs
F3=abd+ab’c’+bc
Example: 4x3 PLA, 6 product
terms
 Compact Representation

The device is
programmed by
keeping only the
connections that
are actually
needed. It can
perform any 4-
input
combinational
logic functions
that can be written as sums of products using a total of
six or fewer distinct product terms.
Example
 6.3.2 Programmable Array
Logic Devices
A PAL is a special case of a PLA in which the AND
array is programmable but the OR array is fixed.

I1
fixed
F1

F4 Outputs

F5

An unprogrammed
I2
F8 PAL
 A Programmable PAL

Using fuses to program the AND array of PAL.

I1
F1

F4 I1I2’ + I1’I2

F5

A programmed
I2
F8 PAL
Logic diagram of the PAL16L8

………
 6.3.3 Generic Array Logic
Devices
Generic Array Logic (GAL) is one type of sequential
PLD which was first introduced by Lattice
Semiconductor.
Here we study the logic diagram for GAL16V8 when
it has been configured as a strictly combinational
device similar to the PAL16L8.

Combinational
output logic
macrocells for
the GAL16V8
Logic diagram of the GAL16L8C

………
Combinational Logic
Building Blocks
 Decoders
 Binary n-to-2n decoders.
 Implementing functions using
decoders.
 Encoders
 2n -to-n binary encoders.
 Multiplexers
 Demultiplexers
 6.4 Decoders
 A decoder is a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and
output codes are different.
e.g. n-to-2n, BCD decoders.
 Enable inputs must be on for the decoder to function, otherwise
its outputs assume a single “disabled” output code word.

Decoder
Input
Code word
Output
Map code word
Enable
inputs
 6.4.1 Binary Decoders
 A binary decoder has n inputs and 2n outputs (n-
to-2n Decoders).
 Only the output corresponding to the input value
equals 1.

n n to 2n 2n
inputs : decoder outputs
:
 2-to-4 Binary Decoder

X Y F0 F1 F2 F3
0 0 1 0 0 0 F0 = X'Y'
Truth Table: 0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 F1 = X'Y
 From truth table, circuit for
2x4 decoder is: F2 = XY'
 Note: Each output is a 2-
variable minterm (X'Y', X'Y, F3 = XY
XY' or XY)

F0
X 2-to-4 F1 X Y
Y Decoder F2
F3
6.4.2 Logic Symbols for Larger-Scale

Elements

 Input

 Output

 Active level
6.4.3 Gate-level circuit diagram

3-to-8 decoder
Truth table for a 74x138 3-to-8 decoder
74x139 Decoder
 More decoder symbols

Preferred Correct but to Incorrect because

symbol be avoided double negations
 6.4.4 Cascading Binary Decoders

4-to-16 decoder
More
Cascading

5-to-32 decoder
 6.4.6 Decoder in VHDL

VHDL structural program for a 2-to-4 binary decoder

library IEEE;
use IEEE.std_logic_1164.all;

entity V2to4dec is
port (I0, I1, EN: in STD_LOGIC;
Y0, Y1, Y2, Y3: out STD_LOGIC);
end V2to4dec;
architecture V2to4dec_s of V2to4dec is
VHDL for 3-to-8 decoder
signal NOTI0, NOTI1: STD_LOGIC;
component inv port (I: in STD_LOGIC; O: out STD_LOGIC);
end component;
component and3 port (I0, I1, I2: in STD_LOGIC; O: out STD_LOGIC);
end component;
begin
U1: inv port map (I0, NOTI0);
U2: inv port map (I1, NOTI1);
U3: and3 port map (NOTI0, NOTI1, EN, Y0);
U4: and3 port map ( I0, NOTI1, EN, Y1 );
U5: and3 port map (NOTI0, I1, EN, Y2);
U6: and3 port map ( I0, I1, EN, Y3 );
end V2to4dec_s;
 Dataflow-style VHDL program
for a 3-to-8 binary decoder
library IEEE;
use IEEE.std_logic_1164.all;

entity V74x138 is
port (
G1: in STD_LOGIC; --enable inputs
G2A_L: in STD_LOGIC;
G2B_L: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (2 downto 0); --select inputs
Y_L: out STD_LOGIC_VECTOR (0 to 7) --decoded outputs
);
end V74x138;
architecture V74x138_a of V74x138 is
signal Y_L_i: STD_LOGIC_VECTOR (0 to 7);
begin VHDL for 3-to-8 decoder
with A select Y_L_i <=
"01111111" when "000",
"10111111" when "001",
"11011111" when "010",
"11101111" when "011",
"11110111" when "100",
"11111011" when "101",
"11111101" when "110",
"11111110" when "111",
"11111111" when others;
Y_L <= Y_L_i when (G1 and not G2A_L and not G2B_L)='1' else
"11111111";
end V74x138_a;
6.4.x Supplementary examples
—— Implement logic function using Decoder

Question: Implement the following logic functions using

4-to-16 Decoder and NAND circuits.
(1) F ( A, B, C , D )   (0,1,5,7,10)
( 2) F  ABCD  ABD  ACD
Solution
: Represent the logic function as canonical sum
(sum of the minterms).

Connect outputs of decoder corresponding to

each minterm with NAND.
 Solution
(1) F ( A, B, C , D )   (0,1,5,7,10)
 m0  m1  m5  m7  m10
A
f0  ( m0 'm1 'm5 'm7 'm10 ' )'
f1
B
4to16 F
C Dec f
5
f7
D
f10
G1 G2A G2B

1
 Solution
( 2) F  ABCD  ABD  ACD
 ABCD  ABCD  ABC’D  ABCD  AB’
CD
  (11,13,15)
f0
A

B
4to16
F
C Dec f
11
f13
D
f15
G1 G2A G2B

1
 6.5 Encoders
 If a decoder's output code has fewer bits than the input code, the
device is usually called an encoder.
e.g. 2n-to-n, priority encoders.
 The simplest encoder is a 2n-to-n binary encoder, where it has only
one of 2n inputs = 1 and the output is the n-bit binary number
corresponding to the active input.
 For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions
of the outputs Y0-Y2 are:
Binary
Y0 = I1 + I3 + I5 + I7 2n .
encoder
. n
Y1 = I2 + I3 + I6 + I7 inputs . . outputs
. .
Y2 = I4 + I5 + I6 + I7
 8-to-3 Binary
Encoder Inputs Outputs
I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
At any one time, only 0 0 1 0 0 0 0 0 0 1 0
one input line has a 0 0 0 1 0 0 0 0 0 1 1
value of 1. 0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
I0
I1 Y2 = I 4 + I 5 + I 6 + I 7
I2
I3 Y1 = I 2 + I 3 + I 6 + I 7

I4
I5
I6 Y0 = I 1 + I 3 + I 5 + I 7
I7
 Priority Encoders

8-input priority encoder

Input I7 has the highest
priority.

We want to report the number

of the highest-priority asserted
input.
We also want to report when
there are no requests.
 Priority-encoder logic
equations
First we define eight intermediate variables H0-H7:
H7 = I7
H6 = I6•I7’
H5 = I5•I6’•I7’
•••
H0 = I0•I1’•I2’•I3’•I4’•I5’•I6’•I7’
Using these signals, the equations for the A2-A0 out-
puts are similar to the ones for a simple binary encoder:
A2 = H4 + H5 + H6 + H7
A1 = H2 + H3 + H6 + H7
A0 = H1 + H3 + H5 + H7
Finally:
IDLE = I0’•I1’•I2’•I3’•I4’•I5’•I6’•I7’
74x148 8-input priority
encoder

Active-low I/0
Enable Input
Group Select or “Got Something” Output
Enable Output (to connect with EI of lower priority encoders)
74x148 Truth Table
74x148
Circuit
 1
1 1
1 1
1 1
1
0
1
1
0 1

 32-input 1
1
1

priority encoder 16
1
1
1

1
8
1
0
1
1 4
Cascading 1
1
2
0
Priority
Encoders 1
0
1 1
1
1

1 1
1