Lecture 9

Exception Handling (continue)

Today’s topics
• Exception vector table
• Detail steps on exception handling
• Interrupt source
– External Interrupt
Exception Priorities
When multiple exceptions occur at the same time
SWI handler  
Exceptions Priority I bit F bit
1 1
…  
Reset Highest priority
IRQ handler  

Data Abort 1 - …  

FIQ 1 1 FIQ 0x1C

1 - IRQ 0x18
IRQ
Reserved 0x14
Pre-fetch 1 -
Data Abort 0x10
SWI Lowest priority 1 -
Prefetch Abort 0x0C
Undefined instructions Lowest priority 1 -
Software Interrupt 0x08
Undefined Instruction 0x04
Reset 0x00
Note: SWI and undefined instruction have the same level of priority
because they cannot occur simultaneously
What’s in LPC2300_v2.s?
Vectors LDR PC, Reset_Addr;0x00
LDR PC, Undef_Addr;0x04
LDR PC, SWI_Addr ;0x08
LDR PC, PAbt_Addr ;0x0C
LDR PC, DAbt_Addr ;0x0F
NOP ;0x14 Reserved Vector
LDR PC, IRQ_Addr ;0x18
;LDR PC, [PC, #-0x0120] ;0x18
LDR PC, FIQ_Addr ;0x1C

Reset_Addr DCD Reset_Handler ;code for Reset_Handler is in LPC2300_v2.s

Undef_Addr DCD Undef_Handler ;code for Undef_Handler is in exceptions.s
SWI_Addr DCD SWI_Handler ;code for SWI_Handler is in exceptions.s
PAbt_Addr DCD PAbt_Handler ;code for PAbt_Handler is in exceptions.s
DAbt_Addr DCD DAbt_Handler ;code for DAbt_Handler is in exceptions.s
DCD 0 ;Reserved Address
IRQ_Addr DCD IRQ_Handler ;code for IRQ_Handler is in exceptions.s
FIQ_Addr DCD FIQ_Handler ;code for FIQ_Handler is in exceptions.s
Example: an interrupt handler
00000014 ...
00000018 B irq_handler ; “address for irq”
0000001C ...

irq_handler
... ;code to handle the irq
...
...
SUBS PC, R14, #4 ;Restore and return
Exception Handlers

• The exception handler is written by a programmer.

• It’s up to the programmer how to handle that exception.
– Trap the exception
– Resolve the exception
– Reset the processor
Exception vector table

• Each exception has its own assigned memory address shown above.
• Each address contains information (an instruction) where each exception
handler is.
Reset handler
• Initializes the system, setting up stack pointers, memory,
external interrupt sources before enabling IRQ or FIQ, …
• It is the first thing executed by the processor. When it first
receives power or its reset is activated, 0x00000000 is put on
the address bus to access the memory where the first
instruction is.
• Once it finishes, the processor will go to the main routine
(code).
Undefined Instruction
• Instruction format that falls in Undefined group
• Specialty instructions that are only valid in certain
ARM process variants.

Source: ARM Architecture Reference Manual

SWI
• Generated by instruction SWI
• The execution of an instruction causes the
exception.
• Forces the processor into SVC mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cond 1 1 1 1 SWI number

Pre-fetch exception
Memory fault during the instruction fetch.
• Memory does not exist.
• The address is outside of a defined memory area.
• Occurs when an attempt to fetch an instruction results in
memory fault.
• It can sometimes be helped with hardware (memory
management unit) if the core has the unit.
• Invalid instruction.
Data Abort exception
Memory fault during data transfers (load or store)
• Occurs when memory controller indicates that an invalid
memory address has been accessed
• Try to write into an only-readable memory area
• The address is outside of a defined memory area.
• It can sometimes be helped with hardware (memory
management unit) if the core has the unit.
FIQ
• FIQ is reserved for an interrupt source which requires fast
response time and needs attention or needs to be serviced
immediately
– Power cut off
– Drop proofing hard disk
– Brushless DC motor commutation control

• The current instruction (when FIQ occurs) will be completed

first before the processor will go to the FIQ handler.
On an FIQ interrupt
On an FIQ interrupt, the processor will ...
• If the “F” bit in the CPSR is clear and the current
instruction is completed, the ARM will
– Save the address of the next instruction plus 4 in r14_fiq
– Save the CPSR in the SPSR_fiq
– Force the CPSR mode bits M[4:0] to 10001 (binary)

• This switches the CPU to FIQ mode and then sets the “I” and
“F” flags to disable further IRQ or FIQ interrupts

• PC is changed to the appropriate exception ‘vector’ address

IRQ
• IRQ is normally assigned to general purpose interrupts
– Periodic timer
– External interrupt
– Serial communication

• Use more often than FIQ

• The current instruction (when IRQ occurs) will be

completed first before the processor will go to the FIQ
handler

IRQ: IRQ handler will be entered if neither an FIQ exception nor Data abort exception occurs.
On entry, IRQ exception is disabled and should remain disabled for the handler.
Exception Handling
Exception Handlers

• The exception handler is written by a programmer.

• It’s up to the programmer how to handle that exception.
– Trap the exception
– Resolve the exception
– Reset the processor
How to go from here to there?
0x400 SWI_handler  Branch instruction
… – B SWI_handler
0x200 IRQ_handler
…
0x1C FIQ  MOV instruction
0x18 IRQ
– MOV PC, #0x200
0x14 Reserved
0x10 Data Abort
0x0C
0x08
Prefetch Abort
Software Interrupt
 LDR instruction
0x04 Undefined Instruction – LDR PC,
0x00 Reset [PC+offset]
Example: an interrupt handler
00000010 ...
00000014 ...
00000018 B irq_handler ; “address for irq”
0000001C ...

irq_handler
... ;code to handle the irq
...
...
SUBS PC, R14, #4 ;Restore and return
On an IRQ interrupt
On an IRQ interrupt, the processor will ...
• If the “I” bit in the CPSR is clear, the current instruction is
completed and then the ARM will
– Save the address of the next instruction plus 4 in r14_irq
– Save the CPSR in the SPSR_irq
– Force the CPSR mode bits M[4:0] to 10010 (binary)

• This switches the CPU to IRQ mode and then sets the “I” flag
to disable further IRQ interrupts.

• PC is changed to the appropriate exception ‘vector’ address

Entering Exception Handler
When an exception occurs, ARM completes the current instruction (except in
a reset mode) and then performs the following sequence of actions
automatically:
1. Copy the current value of CPSR register into SPSR_xxx register.
2. The appropriate bits of CPSR are changed (including disable appropriate interrupt)
– mode (bits 4-0 of CPSR) are changed depending on the new exception mode.
– IRQ interrupts (bit 7) are disabled on entry to all exceptions.
– FIQ interrupts (bit 6) are disabled on entry to reset and FIQ.
3. Save the return address in r14_xxx
4. Change PC to the appropriate exception ‘vector’ address
5. At this point, the processor begins executing code in the exception handler.
Executing the exception handler

After PC (R15) is changed to the corresponding exception vector

address, the processor begins executing code in the exception
handler (a block of code written specifically to deal with each
exception).
Returning from Exception Handler
Once finishes executing code in the exception handler,
the processor should return to where it came from (except for reset
handler).

A few things that must be done by the handler are

 Clear the source of the interrupt (It should always be done
within the handler)
 CPSR is restored from SPSR_xxx.
 PC is restored from r14_xxx.
 (optional) restore any modified user registers from the handler’s
stack
Interrupt Source
Interrupt Sources

Source: ARM Architecture Reference Manual (UM10211 Rev4.1)

Interrupt Sources

This register controls which of the 32 interrupt requests and

software interrupts are enabled to contribute to FIQ or IRQ
External Interrupt
LPC2378 Interrupts
• Every pin of PORT0 and 2 can be configured as an edge-
sensing interrupt (UM10211, ch 10.5.6)
• Four external interrupt inputs (P2.10 to P2.13)
– The EXTINT register contains the interrupt flags.
– The EXTMODE and EXTPOLAR registers specify the level and edge
sensitivity parameters.

Source: ARM Architecture Reference Manual (UM10211 Rev4.1)

External Interrupt

Source: ARM Architecture Reference Manual (UM10211 Rev4.1)

External interrupt function

Source: ARM Architecture Reference Manual (UM10211 Rev4.1)

External Interrupt flag register (EXTINT)

Source: ARM Architecture Reference Manual (UM10211 Rev4.1)

External Interrupt Mode register (EXTMODE)

Source: ARM Architecture Reference Manual (UM10211 Rev4.1)

External Interrupt Mode register (EXTMODE)

Source: ARM Architecture Reference Manual (UM10211 Rev4.1)

External interrupt
• When a pin is selected for its external interrupt function, the level or edge
on that pin (selected by its bits in the EXTPOLAR and EXTMODE registers)
will set its interrupt flag in this register.
• This asserts the corresponding interrupt request to the VIC, which will
cause an interrupt if interrupts from the pin are enabled.
• Once a bit from EINT0 to EINT3 is set and an appropriate code starts to
execute (handling wakeup and/or external interrupt), this bit in EXTINT
register must be cleared. Otherwise event that was just triggered by
activity on the EINT pin will not be recognized in future.
• Writing 1 to bits EINT0 through EINT3 in EXTINT register clears the
corresponding bits.
In level-sensitive mode the interrupt is cleared only when the pin is in its
inactive state.
Read textbook Ch. 11.8.3.1
Just 3 pages of text.

For those who go above and beyond:

Read Ch. 6 (LPC23xx user manual – UM10211)