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L8 - ARM Addressing Modes

The document discusses ARM addressing modes and instruction formats. It describes 12 addressing modes including immediate, register, scaled register, PC relative, immediate offset, register offset, scaled register offset, and pre-indexed and post-indexed variations. It also explains the 32-bit immediate field and how it represents constants. Finally, it provides an overview of the ARM instruction format.

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rameshvibhin poosarla
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49 views

L8 - ARM Addressing Modes

The document discusses ARM addressing modes and instruction formats. It describes 12 addressing modes including immediate, register, scaled register, PC relative, immediate offset, register offset, scaled register offset, and pre-indexed and post-indexed variations. It also explains the 32-bit immediate field and how it represents constants. Finally, it provides an overview of the ARM instruction format.

Uploaded by

rameshvibhin poosarla
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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ARM Addressing for 32-Bit Immediate

and More Complex Addressing Modes


32-Bit Immediate Operands
• Constants are frequently short and fit into a narrow
field
• Sometimes they are bigger
• 32-bit constants were more popular than others so
included in ARM
• 12-bit operand2 field in the DP format is subdivided
into two fields:
– 8-bit constant field on the right
– 4-bit rotate right field (rotates the 8-bit constant to the
right by twice the value in the rotate field
• Number is represented as X * 22i
• 0 < X < 255 & 0 < i < 15
Loading a 32-bit Constant
• ARM machine code to load 32-bit constant into register r0?
• 0000 0000 1101 1001 0000 0000 0000 0000 = 1422131210
• 8-bit constant field = 1101 1001 = D910 = 21710
• 4- bit rotate field = 8 (rotated right by 16 bits)
• X * 22i = 217 * 22*8 = 217 * 216 = 217 * 65536 = 1422131210
• MOV r0, D9 ROR 16

Cond F I Opcode S Rn Rd Rotate_imm mm_8

14 0 1 13 0 0 4 8 217
Addressing Modes
• There are different ways to specify the address of the
operands for any given operations (load, add or branch)
• Addressing modes - The different ways of determining the
address of the operands
• Information contained in the instruction code is the value of
the operand or the address of the result/operand
Addressing Modes (1)
1. Immediate Addressing
• The operand is a constant within the instruction itself
• ADD r2, r0, #5 ; r2 = r0+5
• CMP r0, #1 ; r0 – 1
• MOV r1, #1 ; r1 = 1

2. Register Addressing
• Operand is a register
• ADD r2, r0, r1

3. Scaled Register Addressing


• Register operand is shifted prior to operation
• ADD r2, r0, r1, LSL #2
Immediate Addressing , Register Addressing
Addressing Modes (2)
4. PC Relative Addressing
• Branch address is the sum of the PC and a constant in the
instruction
• BEQ 1000

5. Immediate offset
• Constant address is added to a base register
• LDR r2, [r0, #8]

6. Register Offset
• Another register is added to the base register
• Array index is in one register and base of the array is in another
• LDR r2, [r0, r1]
Addressing Modes (3)
7. Scaled Register Offset
• Allows the register to be shifted before it is added to the base register
• Useful to turn array index in to a byte address by shifting it left by 2
bits
• LDR r2, [r0, r1, LSL #2]

8. Immediate offset Pre-Indexed


• Facilitate the reading of sequential data in structures such as arrays,
tables, and vectors
• A pointer register is used to hold the base address (r0)
• An offset can be added to achieve the effective address
• LDR r2, [r0, #4] ; Effective Address r0+4
• Loads r2 with the word pointed at by r0+4 ; then update the pointer
by adding 4 to r0
Addressing Modes (4)
9. Immediate offset Post-indexed
• Address in the base register is used to access memory first
• Then constant is added or subtracted
• LDR r2, [r0], #4

10. Register offset Pre-indexed


• Same as immediate pre indexed except add or subtract a
register instead of a constant
• LDR r2, [r0, r1] !
Addressing Modes (5)
11. Scaled Register offset Pre indexed
• Same as register pre indexed except shift the register before
adding or subtracting it
• LDR r2, [r0, r1, LSL #2]!

12. Register offset Post indexed


• Same as immediate post indexed except add or subtract a
register instead of a constant
• LDR r2, [r0], r1
ARM Instruction Formats

• The top 4 bits [31:28] are used to specify the conditions under
• which the instruction is executed
• Bits [27:25] identify this as a B or BL instruction
• The L-bit (bit 24) is set if it is a branch with link instruction and clear if it is
a plain branch
• 24-bit signed offset specifies destination of branch in 2's complement form

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