Computer Architecture

A Quantitative Approach, Fifth Edition

Chapter 2
Memory Hierarchy Design

Copyright © 2012, Elsevier Inc. All rights reserved. 1

 Introduction
Introduction
 Programmers want unlimited amounts of memory with
low latency
 Fast memory technology is more expensive per bit than
slower memory
 Solution: organize memory system into a hierarchy
 Entire addressable memory space available in largest, slowest
memory
 Incrementally smaller and faster memories, each containing a
subset of the memory below it, proceed in steps up toward the
processor
 Temporal and spatial locality insures that nearly all
references can be found in smaller memories
 Gives the allusion of a large, fast memory being presented to the
processor

Copyright © 2012, Elsevier Inc. All rights reserved. 2

 Introduction
Memory Hierarchy

Copyright © 2012, Elsevier Inc. All rights reserved. 3

 Introduction
Memory Performance Gap

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 Introduction
Memory Hierarchy Design
 Memory hierarchy design becomes more crucial
with recent multi-core processors:
 Aggregate peak bandwidth grows with # cores:
 Intel Core i7 can generate two references per core per clock
 Four cores and 3.2 GHz clock
 25.6 billion 64-bit data references/second +

 12.8 billion 128-bit instruction references

 = 409.6 GB/s!

 DRAM bandwidth is only 6% of this (25 GB/s)

 Requires:
 Multi-port, pipelined caches
 Two levels of cache per core
 Shared third-level cache on chip

Copyright © 2012, Elsevier Inc. All rights reserved. 5

 Introduction
Performance and Power
 High-end microprocessors have >10 MB on-chip
cache
 Consumes large amount of area and power budget

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 Introduction
Memory Hierarchy Basics
 When a word is not found in the cache, a miss
occurs:
 Fetch word from lower level in hierarchy, requiring a
higher latency reference
 Lower level may be another cache or the main
memory
 Also fetch the other words contained within the block
 Takes advantage of spatial locality
 Place block into cache in any location within its set,
determined by address
 block address MOD number of sets

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 Memory Hierarchy Basics
• Hit: data appears in some block in the upper level
(example: Block X)
– Hit Rate: the fraction of memory access found in the upper level
– Hit Time: Time to access the upper level which consists of
RAM access time + Time to determine hit/miss
• Miss: data needs to be retrieved from a block in the
lower level (Block Y)
– Miss Rate = 1 - (Hit Rate)
– Miss Penalty: Time to replace a block in the upper level +
Time to deliver the block the processor
• Hit Time << Miss Penalty (500 instructions on 21264!)
Lower Level
To Processor Upper Level Memory
Memory
Blk X
From Processor Blk Y
 Introduction
Memory Hierarchy Basics
 n blocks per set => n-way set associative
 Direct-mapped cache => one block per set (one-way)
 Fully associative => one set
 Place block into cache in any location within its set,
determined by address
 block address MOD number of sets
 Writing to cache: two strategies
 Write-through
 Immediately update lower levels of hierarchy
 Write-back
 Only update lower levels of hierarchy when an updated block
is replaced
 Both strategies use write buffer to make writes
asynchronous

Copyright © 2012, Elsevier Inc. All rights reserved. 9

 Q4: What happens on a write?
Write-Through Write-Back
Write data only to the
Data written to cache cache
block
Policy
also written to lower- Update lower level
level memory when a block falls out
of the cache

Debug Easy Hard

Do read misses
produce writes? No Yes
Do repeated writes
make it to lower Yes No
level?

Additional option (on miss)-- let writes to an un-cached address;

allocate a new cache line (“write-allocate”).
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Hierarchy Introduction
Write Buffers for Write-Through Caches

Cache Lower
Processor Level
Memory

Write Buffer

Holds data awaiting write-through to

lower level memory
Q. Why a write buffer ? A. So CPU doesn’t stall
Q. Why a buffer, why not A. Bursts of writes are
just one register ? common.
Q. Are Read After Write A. Yes! Drain buffer before
(RAW) hazards an issue next read, or send read 1st
for write buffer? after check write buffers.
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Hierarchy Introduction
Memory Hierarchy Basics
• Hit rate: fraction found in that level
– So high that usually talk about Miss rate
– Miss rate fallacy: as MIPS to CPU performance,
miss rate to average memory access time in memory
• Average memory-access time
= Hit time + Miss rate x Miss penalty
(ns or clocks)
• Miss penalty: time to replace a block from
lower level, including time to replace in CPU
– access time: time to lower level
= f(latency to lower level)
– transfer time: time to transfer block
=f(BW between upper & lower levels, block size)

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Hierarchy Introduction
 Introduction
Memory Hierarchy Basics
 Miss rate
 Fraction of cache access that result in a miss

 Causes of misses
 Compulsory
 First reference to a block, also called “cold miss”
 Capacity
 Blocks discarded (lack of space) and later retrieved
 Conflict
 Program makes repeated references to multiple addresses
from different blocks that map to the same location in the
cache

Copyright © 2012, Elsevier Inc. All rights reserved. 13

 Introduction
Memory Hierarchy Basics

 Note that speculative and multithreaded

processors may execute other instructions
during a miss
 Reduces performance impact of misses

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 Improve Cache Performance
improve cache and memory access times:

Average Memory Access Time = Hit Time + Miss Rate * Miss Penalty

Reducing each of these!

Simultaneously?

CPUtime  IC * (CPI Execution  MemoryAcce ss

Instruction * MissRate * MissPenalt y * ClockCycle Time )

 Improve performance by:

1. Reduce the miss rate,
2. Reduce the miss penalty, or
3. Reduce the time to hit in the cache.

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Hierarchy Introduction
 Introduction
Memory Hierarchy Basics
 Six basic cache optimizations:
 Larger block size
 Reduces compulsory misses
 Increases capacity and conflict misses, increases miss penalty
 Larger total cache capacity to reduce miss rate
 Increases hit time, increases power consumption
 Higher associativity
 Reduces conflict misses
 Increases hit time, increases power consumption
 Higher number of cache levels
 Reduces overall memory access time
 Giving priority to read misses over writes
 Reduces miss penalty
 Avoiding address translation in cache indexing
 Reduces hit time

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The Limits of Physical Addressing
“Physical addresses” of memory locations

A0-A31 A0-A31

CPU Memory
D0-D31 D0-D31

Data
oAll programs share one address space:
The physical address space
oMachine language programs must be
aware of the machine organization
oNo way to prevent a program from
accessing any machine resource
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Hierarchy Introduction
Solution: Add a Layer of Indirection
“Virtual Addresses” “Physical Addresses”
A0-A31 A0-A31
Virtual Physical

CPU Address Memory

Translation
D0-D31 D0-D31

Data
• User programs run in a standardized
virtual address space
• Address Translation hardware, managed
by the operating system (OS), maps
virtual address to physical memory
• Hardware supports “modern” OS features:
Protection, Translation, Sharing
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Hierarchy Introduction
 Three Advantages of Virtual Memory
• Translation:
– Program can be given consistent view of memory, even though physical
memory is scrambled
– Makes multithreading reasonable (now used a lot!)
– Only the most important part of program (“Working Set”) must be in
physical memory.
– Contiguous structures (like stacks) use only as much physical memory
as necessary yet still grow later.
• Protection:
– Different threads (or processes) protected from each other.
– Different pages can be given special behavior
» (Read Only, Invisible to user programs, etc).
– Kernel data protected from User programs
– Very important for protection from malicious programs
• Sharing:
– Can map same physical page to multiple users
(“Shared memory”)

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Hierarchy Introduction
 Page tables encode virtual address spaces
Physical
Page Table
Memory Space A virtual address space
frame
is divided into blocks
frame
of memory called pages
frame
frame A machine
usually supports
virtual pages of a few
address
sizes
(MIPS R4000):
OS manages A page table is indexed by a
the page virtual address
table for
each ASID
A
(Addr. Space valid page table entry codes physical memory
ID) “frame” address for the page
 An Example of Page Table
Virtual Memory
Physical Memory

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 Dividing the address space by a page size
Virtual Memory
Physical Memory

Page size:4KB
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Hierarchy Introduction
 Virtual Page & Physical Page
Virtual Memory
V.P. 0 Physical Memory
P.P. 0
V.P. 1
P.P. 1
V.P. 2
P.P. 2
V.P. 3
P.P. 3
V.P. 4

V.P. 5

Page size:4KB
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Hierarchy Introduction
 Addressing
Virtual Memory Virtual Address
V.P. 0 Virtual Page No. P. Offset Physical Memory
P.P. 0
V.P. 1
P.P. 1
V.P. 2
P.P. 2
V.P. 3
P.P. 3
V.P. 4
Physical Address
V.P. 5
Physical Page No. P. Offset

Page size:4KB
CSCE 430/830, Memory
Hierarchy Introduction
 Addressing
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

Page Table Entry

Physical Address
Physical Page No. P. Offset

CSCE 430/830, Memory

Hierarchy Introduction
 Addressing
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

Page Table Entry

V P R D Physical Page No.

Valid/Present Bit
If set, page being pointed is
resident in memory
Otherwise, on disk or not
allocated
Physical Address
Physical Page No. P. Offset

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Hierarchy Introduction
 Addressing
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

Page Table Entry

V P R D Physical Page No.

Protection Bits
Restrict access;
read-only, read/write, system-
only access

Physical Address
Physical Page No. P. Offset

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Hierarchy Introduction
 Addressing
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

Page Table Entry

V P R D Physical Page No.

Reference Bit
Needed by replacement policies
If set, page has been referenced

Physical Address
Physical Page No. P. Offset

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 Page Table Entry
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

Page Table Entry

V P R D Physical Page No.

Dirty Bit
If set, at least one word in page
has been modified

Physical Address
Physical Page No. P. Offset

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Hierarchy Introduction
 Page Table Entry
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

V P R D Physical Page No.

V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.

Physical Page No. P. Offset Physical Address

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Hierarchy Introduction
 Page Table Lookup
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

virtual address

V P R D Physical Page No.

V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.

Physical Page No. P. Offset Physical Address

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Hierarchy Introduction
 Page Table Lookup
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

virtual address

V P R D Physical Page No.

V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.

Physical Page No. P. Offset Physical Address

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Hierarchy Introduction
 Page Table Lookup
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

virtual address

V P R D Physical Page No.

V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.

Physical Page No. P. Offset Physical Address

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Hierarchy Introduction
 Page Table Lookup
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

virtual address

V P R D Physical Page No.

V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.

Physical Page No. P. Offset Physical Address

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Hierarchy Introduction
 Page Table Lookup
Virtual Memory Virtual Address
Virtual Page No. P. Offset
Physical Memory

virtual address

physical address
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.
V P R D Physical Page No.

Physical Page No. P. Offset

Physical Address
CSCE 430/830, Memory
Hierarchy Introduction
 Details of Page Table
Page Table Physical
Memory Space Virtual Address
12
frame V page no. offset
frame
frame Page Table
frame Page Table
Base Reg Access
index V Rights PA
into
page
virtual
table table located
address in physical P page no. offset
memory 12
Physical Address
• Page table maps virtual page numbers to physical
frames (“PTE” = Page Table Entry)
• Virtual memory => treat memory  cache for disk
• 4 fundamental questions: placement, identification,
replacement, and write policy?
4 Fundamental Questions
• Placement
– Operating systems allow blocks to be
placed anywhere in main memory
• Identification
– Page Table, Inverted Page Table
• Replacement
– Almost all operating systems try to use
LRU
• Write Policies
– Always write back

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Latency
• Since Page Table is located in main memory, it
takes one memory access latency to finish an
address translation;
• As a result, a load/store operation from/to main
memory needs two memory access latency in
total;
• Considering the expensive memory access
latency, the overhead of page table lookup
should be optimized;
• How?
– Principle of Locality
– Caching

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Hierarchy Introduction
MIPS Address Translation: How does it work?
“Virtual Addresses” “Physical Addresses”

A0-A31 Virtual Physical A0-A31

Translation
CPU Look-Aside Memory
Buffer
D0-D31 (TLB) D0-D31

Data What is the

table of
Translation Look-Aside Buffer (TLB) mappings
A small fully-associative cache of that it
mappings from virtual to physical addresses caches?
TLB also contains
protection bits for virtual address
Fast common case: Virtual address is in TLB,
process has permission to read/write it.
 The TLB caches page table entries
Physical and virtual
pages must be the same
size!
LB caches page
table entries. Physical
virtual address for ASID
frame
page off address
Page Table

1
3 V=0 pages either
physical address
reside on disk or
page off
TLB have not yet been
frame page MIPS handles TLB misses in allocated.
2 2 software (random
0 5 replacement). Other machines OS handles V=0
use hardware. “Page fault”
 Can TLB and caching be overlapped?
Virtual Page Number Page Offset

Virtual
Index Byte Select

Translation
Look-Aside Cache Tags Valid Cache Data
Buffer
(TLB) Cache Block

Physical
Cache Tag = Cache Block

Hit
This works, but ...
Q. What is the downside?
A. Inflexibility. Size of cache
limited by page size.
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Hierarchy Introduction
 8

VA: 64bits
PA: 40bits
Page size: 16KB
TLB: 2-way set
associative, 256
entries
Cache block: 64B
L1: direct-mapping,
16KB
L2: 4-way set
associative, 4MB
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Hierarchy Introduction
 Advanced Optimizations
Ten Advanced Optimizations
 Small and simple first level caches
 Critical timing path:
 addressing tag memory, then
 comparing tags, then
 selecting correct set
 Direct-mapped caches can overlap tag compare and
transmission of data
 Lower associativity reduces power because fewer
cache lines are accessed

Copyright © 2012, Elsevier Inc. All rights reserved. 43

 Advanced Optimizations
L1 Size and Associativity

Access time vs. size and associativity

Copyright © 2012, Elsevier Inc. All rights reserved. 44

 Advanced Optimizations
L1 Size and Associativity

Energy per read vs. size and associativity

Copyright © 2012, Elsevier Inc. All rights reserved. 45

 Advanced Optimizations
Way Prediction
 To improve hit time, predict the way to pre-set
mux
 Mis-prediction gives longer hit time
 Prediction accuracy
 > 90% for two-way
 > 80% for four-way
 I-cache has better accuracy than D-cache
 First used on MIPS R10000 in mid-90s
 Used on ARM Cortex-A8
 Extend to predict block as well
 “Way selection”
 Increases mis-prediction penalty

Copyright © 2012, Elsevier Inc. All rights reserved. 46

 Advanced Optimizations
Pipelining Cache
 Pipeline cache access to improve bandwidth
 Examples:
 Pentium: 1 cycle
 Pentium Pro – Pentium III: 2 cycles
 Pentium 4 – Core i7: 4 cycles

 Increases branch mis-prediction penalty

 Makes it easier to increase associativity

Copyright © 2012, Elsevier Inc. All rights reserved. 47

 Advanced Optimizations
Nonblocking Caches
 Allow hits before
previous misses
complete
 “Hit under miss”
 “Hit under multiple
miss”
 L2 must support this
 In general,
processors can hide
L1 miss penalty but
not L2 miss penalty

Copyright © 2012, Elsevier Inc. All rights reserved. 48

 Advanced Optimizations
Multibanked Caches
 Organize cache as independent banks to
support simultaneous access
 ARM Cortex-A8 supports 1-4 banks for L2
 Intel i7 supports 4 banks for L1 and 8 banks for L2

 Interleave banks according to block address

Copyright © 2012, Elsevier Inc. All rights reserved. 49

 Advanced Optimizations
Critical Word First, Early Restart
 Critical word first
 Request missed word from memory first
 Send it to the processor as soon as it arrives
 Early restart
 Request words in normal order
 Send missed work to the processor as soon as it
arrives

 Effectiveness of these strategies depends on

block size and likelihood of another access to
the portion of the block that has not yet been
fetched
Copyright © 2012, Elsevier Inc. All rights reserved. 50
 Advanced Optimizations
Merging Write Buffer
 When storing to a block that is already pending in the
write buffer, update write buffer
 Reduces stalls due to full write buffer
 Do not apply to I/O addresses

No write
buffering

Write buffering

Copyright © 2012, Elsevier Inc. All rights reserved. 51

In-Class Exercises
• In systems with a write-through L1 cache backed by a
write-back L2 cache instead of main memory, a merging
write buffer can be simplified. Explain how this can be
done. Are there situations where having a full write buffer
(instead of the simple version you’ve just proposed) could
be helpful?
– The merging buffer links CPU to the L2 cache. Two CPU
writes cannot merge if they are to different sets in L2. So, for
each new entry into the buffer a quick check on only those
address bits that determine the L2 set number need be
performed at first. If there is no match, then the new entry is
not merged. Otherwise, all address bits can be checked for
a definitive result.
– As the associativity of L2 increases, the rate of false positive
matches from the simplified check will increase, reducing
performance.

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Hierarchy Introduction
 Advanced Optimizations
Compiler Optimizations
 Loop Interchange
 Swap nested loops to access memory in
sequential order

 Blocking
 Instead of accessing entire rows or columns,
subdivide matrices into blocks
 Requires more memory accesses but improves
locality of accesses

Copyright © 2012, Elsevier Inc. All rights reserved. 53

Reducing Cache Misses:
5. Compiler Optimizations

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Reducing Cache Misses:
5. Compiler Optimizations

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Hierarchy Introduction
 Reducing Cache Misses:
5. Compiler Optimizations
• Blocking: improve temporal and spatial locality
a) multiple arrays are accessed in both ways (i.e., row-major and column-major), namely,
orthogonal accesses that can not be helped by earlier methods
b) concentrate on submatrices, or blocks

c) All N*N elements of Y and Z are accessed N times and each element of X is accessed once.
Thus, there are N3 operations and 2N3 + N2 reads! Capacity misses are a function of N and
cache size in this case.

CSCE 430/830, Memory

Hierarchy Introduction
 Reducing Cache Misses:
5. Compiler Optimizations (cont’d)
• Blocking: improve temporal and spatial locality
a) To ensure that elements being accessed can fit in the cache, the original code is
changed to compute a submatrix of size B*B, where B is called the blocking factor.
b) To total number of memory words accessed is 2N3//B + N2
c) Blocking exploits a combination of spatial (Y) and temporal (Z) locality.

CSCE 430/830, Memory

Hierarchy Introduction
 Advanced Optimizations
Hardware Prefetching
 Fetch two blocks on miss (include next sequential block):
overlapping memory access with execution by fetching data
items before processor requests them.

Pentium 4 Pre-fetching

Copyright © 2012, Elsevier Inc. All rights reserved. 58

 Advanced Optimizations
Compiler Prefetching
 Insert prefetch instructions before data is
needed
 Non-faulting: prefetch doesn’t cause
exceptions

 Register prefetch
 Loads data into register
 Cache prefetch
 Loads data into cache

 Combine with loop unrolling and software

pipelining
Copyright © 2012, Elsevier Inc. All rights reserved. 59
Reducing Cache Miss Penalty:
Compiler-Controlled Prefetching
 Compiler inserts prefetch instructions
 An Example
for(i:=0; i<3; i:=i+1)
for(j:=0; j<100; j:=j+1)
a[i][j] := b[j][0] * b[j+1][0]
 16-byte blocks, 8KB cache, 1-way write back, 8-byte
elements; What kind of locality, if any, exists for a and b?
a. 3 100-element rows (100 columns) visited; spatial locality:
even-indexed elements miss and odd-indexed elements hit,
leading to 3*100/2 = 150 misses
b. 101 rows and 3 columns visited; no spatial locality, but
there is temporal locality: same element is used in ith and (i
+ 1)st iterations and the same element is access in each i
iteration (outer loop). 100 misses for b[j+1][0] when i = 0
and 1 miss for j = 0 for a total of 101 misses
 Assuming large penalty (100 cycles and at least 7
iterations must be prefetched). Splitting the loop into
two, we have
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Hierarchy Introduction
Reducing Cache Miss Penalty:
3. Compiler-Controlled Prefetching
 Assuming that each iteration of the pre-split loop
consumes 7 cycles and no conflict and capacity misses,
then it consumes a total of 7*300 iteration cycles +
251*100 cache miss cycles = 27,200 cycles;
 With prefetching instructions inserted:
for(j:=0; j<100; j:=j+1){
prefetch(b[j+7][0];
prefetch(a[0][j+7];
a[0][j] := b[j][0] * b[j+1][0];};
for(i:=1; i<3; i:=i+1)
for(j:=0; j<100; j:=j+1){
prefetch(a[i][j+7];
a[i][j] := b[j][0] * b[j+1][0]}
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Hierarchy Introduction
 Reducing Cache Miss Penalty:
3. Compiler-Controlled Prefetching (cont’d)
 An Example (continued)
 the first loop consumes 9 cycles per iteration (due to the two
prefetch instruction) and iterates 100 times for a total of 900
cycles,
 the second loop consumes 8 cycles per iteration (due to the
single prefetch instruction) and iterates 200 times for a total of
1,600 cycles,
 during the first 7 iterations of the first loop array a incurs 4
cache misses, array b incurs 7 cache misses, for a total of
(4+7)*100=1,100 cache miss cycles,
 during the first 7 iterations of the second loop for i = 1 and i = 2
array a incurs 4 cache misses each, for total of (4+4)*100=800
cache miss cycles; array b does not incur any cache miss in the
second split!
 Total cycles consumed: 900+1600+1100+800= 44000
 Prefetching improves performance: 27200/4400=6.2 folds!

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In-Class Exercises
• As caches increase in size, blocks often increase
in sizes as well.
1. If a large instruction cache has larger data blocks, is there still a
need for prefetching? Explain the interaction between
prefetching and increased block size in instruction caches.
– Program basic blocks are often short (<10 instr.), and thus
program executions does not continue to follow sequential
locations for very long. As block gets larger, program is more
likely to not execute all instructions in the block but branch out
early, making instruction prefetching less attractive.
2. Is there a need for data prefetch instructions when data blocks
get larger?
– Data structures often comprise lengthy sequences of memory
addresses, and program access of data structure often takes the
form of sequential sweep. Large data blocks work well with such
access patterns, and prefetching is likely still of value to the
highly sequential access patterns.

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Hierarchy Introduction
 Advanced Optimizations
Summary

Copyright © 2012, Elsevier Inc. All rights reserved. 64

Homework 2
 A typo in the solution template
 Please answer all the 3 questions in Problem
4 (P2.12)
 Problem 2 (P2.8)
 c. Assuming 64 byte cache blocks and a
single bank.
 A trick here.

Copyright © 2012, Elsevier Inc. All rights reserved. 65

Example
 In an L2 cache, a cache hit takes 0.8ns and a
cache miss takes 5.1ns on average. The
cache hit ratio is 95% while the cache miss
ratio is 5%. Assuming a cycle time is 0.5ns,
compute average memory access time.
 A cache hit takes 0.8/0.5 = 2 cycles, and a
cache miss takes 5.1/0.5 = 11 cycles
 Average memory access cycles =
0.95*2+0.05*11 = 2.45 cycles
 Average memory access time = 2.45*0.5 =
1.225ns
Copyright © 2012, Elsevier Inc. All rights reserved. 66
Homework 2
 Problem 3 (P2.11)
 a. How many cycles would it take to service
an L2 cache miss with and without critical
word first and early restart?
 Problem 4 (P2.12)
 b. “Zeroing memory” => sequential stores

Copyright © 2012, Elsevier Inc. All rights reserved. 67

 Computer Memory Hierarchy

http://www.bit-tech.net/hardware/memory/2007/11/15/the_secrets_of_pc_memory_part_1/3

Copyright © 2012, Elsevier Inc. All rights reserved. 68

 Memory Technology
Memory Technology

 Performance
  metrics
 Latency is concern of cache
 Bandwidth is concern of multiprocessors and I/O
 External approach (e.g., multi-bank memory)
 Internal approach (e.g., SDRAM, DDR)
 Memory latency
 Access time (AT): time between read request and when
desired word arrives
 Cycle time (CT): minimum time between unrelated
requests to memory
 DRAM used for main memory
 Dynamic: Must write after read, must refresh: AT < CT
 SRAM used for cache
 Static: no refresh or read followed by write: AT CT

Copyright © 2012, Elsevier Inc. All rights reserved. 69

 Memory Technology
Memory Technology
 SRAM
 Requires low power to retain bit
 Requires 6 transistors/bit
 DRAM
 Must be re-written after being read
 Must also be periodically refreshed
 Every ~ 8 ms
 Each row can be refreshed simultaneously
 One transistor/bit
 Address lines are multiplexed:
 Upper half of address: row access strobe (RAS)
 Lower half of address: column access strobe (CAS)

Copyright © 2012, Elsevier Inc. All rights reserved. 70

 A SRAM Example

http://en.wikipedia.org/wiki/Static_random_access_memory

Copyright © 2012, Elsevier Inc. All rights reserved. 71

 A DRAM Example

http://en.wikipedia.org/wiki/Dynamic_random-access_memory

Copyright © 2012, Elsevier Inc. All rights reserved. 72

 Memory Technology
Memory Technology
 Amdahl:
 Memory capacity should grow linearly with processor speed
 Unfortunately, memory capacity and speed has not kept
pace with processors

 Some optimizations:
 Multiple accesses to same row
 Synchronous DRAM
 Added clock to DRAM interface and enables pipelining
 Burst mode with critical word first
 Wider interfaces
 Double data rate (DDR)
 Multiple banks on each DRAM device

Copyright © 2012, Elsevier Inc. All rights reserved. 73

 Memory Technology
Memory Optimizations

Copyright © 2012, Elsevier Inc. All rights reserved. 74

 Memory Technology
Memory Optimizations

Copyright © 2012, Elsevier Inc. All rights reserved. 75

 DIMM Dual Inline Memory Module

http://en.wikipedia.org/wiki/DIMM

Copyright © 2012, Elsevier Inc. All rights reserved. 76

 Memory Technology
Memory Optimizations
 DDR:
 DDR2
 Lower power (2.5 V -> 1.8 V)
 Higher clock rates (266 MHz, 333 MHz, 400 MHz)
 DDR3
 1.5 V
 800 MHz
 DDR4
 1-1.2 V
 1600 MHz

 GDDR5 is graphics memory based on DDR3

Copyright © 2012, Elsevier Inc. All rights reserved. 77

 Memory Technology
Memory Optimizations
 Graphics memory:
 Achieve 2-5 X bandwidth per DRAM vs. DDR3
 Wider interfaces (32 vs. 16 bit)
 Higher clock rate
 Possible because they are attached via soldering instead of
socketted DIMM modules

 Reducing power in SDRAMs:

 Lower voltage
 Low power mode (ignores clock, continues to
refresh)

Copyright © 2012, Elsevier Inc. All rights reserved. 78

 Memory Technology
Memory Power Consumption

Copyright © 2012, Elsevier Inc. All rights reserved. 79

 Memory Technology
Flash Memory
 Type of EEPROM
 Must be erased (in blocks) before being
overwritten
 Non volatile
 Limited number of write cycles
 Cheaper than SDRAM, more expensive than
disk
 Slower than SRAM, faster than disk

Copyright © 2012, Elsevier Inc. All rights reserved. 80

Solid State Drive (nowadays)

81
 Comparison

Attribute SSD HDD

Random access time 0.1 ms 5-10 ms
Bandwidth 100-500 MB/s 100 MB/s sequential
Price/GB 0.9$-2$ 0.1$
Size Up to 2TB, 250GB 4TB
common
Power consumption 5 watts Up to 20 watts
Read/write symmetry No Yes
Noise No Yes (spin, rotate)

82
NAND Flash Memory
 Main storage component of Solid State Drive (SSD)
 USB Drive, cell phone, touch pad…

83
 Advantages of NAND flash
 Fast random read (25 us)
 Energy efficiency
 High reliability (no moving parts) compared to harddisks
 Widely deployed in high-end laptops
 Macbook air, ThinkPad X series, touch pad…
 Increasingly deployed in enterprise environment either as a
secondary cache or main storage

84
 Disadvantages of SSD
 Garbage collection (GC) problem of SSD
 Stemmed from the out-of-place update characteristics
 Update requests invalidate old version of pages and then write new
version of these pages to a new place
 Copy valid data to somewhere else (increasing number of IOs)
 Garbage collection is periodically started to erase victim blocks and copy
valid pages to the free blocks (slow erase: 10xW,100xR)
 Blocks in the SSD have a limited number of erase cycles
 100,000 for Single Level Chip (SLC), 5,000-10,000 for Multiple Level Chip
(MLC), can be as low as 3,000
 May be quickly worn out in enterprise environment
 Performance is very unpredictable
 Due to unpredictable triggering of the time-consuming GC process

85
Hybrid Main Memory System
 DRAM + Flash Memory
 Uses small DRAM as a cache to buffer writes
and cache reads by leveraging access locality
 Uses large flash memory to store cold data
 Advantages
 Similar performance as DRAM
 Low power consumption
 Low costs

Copyright © 2012, Elsevier Inc. All rights reserved. 86

 Memory Technology
Memory Dependability
 Memory is susceptible to cosmic rays
 Soft errors: dynamic errors
 Detected and fixed by error correcting codes
(ECC)
 Hard errors: permanent errors
 Use sparse rows to replace defective rows

 Chipkill: a RAID-like error recovery technique

Copyright © 2012, Elsevier Inc. All rights reserved. 87

Chipkill

Copyright © 2012, Elsevier Inc. All rights reserved. 88

Chipkill
 A Redundant Array of Inexpensive DRAM (RAID)
processor chip is directly placed on the memory
DIMM.
 The RAID chip calculates an ECC checksum for
the contents of the entire set of chips for each
memory access and stores the result in extra
memory space on the protected DIMM.
 Thus, when a memory chip on the DIMM fails,
the RAID result can be used to "back up" the lost
data.

Copyright © 2012, Elsevier Inc. All rights reserved. 89

 Virtual Memory and Virtual Machines
Virtual Memory
 Protection via virtual memory
 Keeps processes in their own memory space

 Role of architecture:
 Provide user mode and supervisor mode
 Protect certain aspects of CPU state
 Provide mechanisms for switching between user
mode and supervisor mode
 Provide mechanisms to limit memory accesses
 Provide TLB to translate addresses

Copyright © 2012, Elsevier Inc. All rights reserved. 90

 Virtual Memory and Virtual Machines
Virtual Machines
 Supports isolation and security
 Sharing a computer among many unrelated users
 Enabled by raw speed of processors, making the
overhead more acceptable

 Allows different ISAs and operating systems to be

presented to user programs
 “System Virtual Machines”
 SVM software is called “virtual machine monitor” or
“hypervisor”
 Individual virtual machines run under the monitor are called
“guest VMs”

Copyright © 2012, Elsevier Inc. All rights reserved. 91

Virtual Machine Monitors (VMMs)
• Virtual machine monitor (VMM) or hypervisor is software
that supports VMs
• VMM determines how to map virtual resources to physical
resources
• Physical resource may be time-shared, partitioned, or
emulated in software
• VMM is much smaller than a traditional OS;
– isolation portion of a VMM is  10,000 lines of code

CSCE 430/830, Advanced

02/26/2021 92
Memory Hierarchy
Virtual Machine Monitors (VMMs)

CSCE 430/830, Advanced

02/26/2021 93
Memory Hierarchy
Virtual Machine Monitors (VMMs)

CSCE 430/830, Advanced

02/26/2021 94
Memory Hierarchy
 Virtual Memory and Virtual Machines
Impact of VMs on Virtual Memory
 Each guest OS maintains its own set of page
tables
 VMM adds a level of memory between physical
and virtual memory called “real memory”
 VMM maintains shadow page table that maps
guest virtual addresses to physical addresses
 Requires VMM to detect guest’s changes to its own page
table
 Occurs naturally if accessing the page table pointer is a
privileged operation

Copyright © 2012, Elsevier Inc. All rights reserved. 95

VMM Overhead?
• Depends on the workload
• User-level processor-bound programs (e.g.,
SPEC) have zero-virtualization overhead
– Runs at native speeds since OS rarely invoked
• I/O-intensive workloads  OS-intensive
 execute many system calls and privileged
instructions
 can result in high virtualization overhead
– For System VMs, goal of architecture and VMM is to run
almost all instructions directly on native hardware
• If I/O-intensive workload is also I/O-bound
 low processor utilization since waiting for I/O
 processor virtualization can be hidden
 low virtualization overhead

CSCE 430/830, Advanced

02/26/2021 96
Memory Hierarchy
Q1: Where can a block be placed in the upper level?

• Block 12 placed in an 8-block cache:

– Fully associative, direct mapped, 2-way set associative
– S.A. Mapping = (Block Number) Modulo (Number Sets)
Directly Mapped
Fully Mapped 2-Way Associative
(1-way associative)
(fully associative) (12 mod 4) = 0
(12 mod 8) = 4
01234567 01234567 01234567

Cache

1111111111222222222233
01234567890123456789012345678901

Memory

CSCE 430/830, Memory

Hierarchy Introduction
Direct Mapped Block Placement

Cache

address maps to block:

*0 *4 *8 *C
location = (block address MOD # blocks in cache)

00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C

Memory
Fully Associative Block Placement

Cache

arbitrary block mapping

location = any

00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C

Memory
Set-Associative Block Placement

Cache

address maps to set:

*0 *0 *4 *4 *8 *8 *C *C location = (block address MOD # sets in cache)
(arbitrary location in set)

Set 0 Set 1 Set 2 Set 3

00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C

Memory
Q2: How is a block found if it is in the upper level?

• Tag on each block

– No need to check index or block offset
• Increasing associativity shrinks index, expands
tag

Block Address Block

Tag Index Offset

CSCE 430/830, Memory

Hierarchy Introduction
 Direct-Mapped Cache Design
Cache
ADDRESS Tag Byte Offset DATA HIT =1
Index
0x0000000 3 0
ADDR
V Tag Data
1 0x00001C0 0xff083c2d
0
1 0x0000000 0x00000021
1 SRAM
CACHE 0x0000000 0x00000103
0
0
1
0 0x23F0210 0x00000009
DATA[59] DATA[58:32] DATA[31:0]

=
 Set Associative Cache Design

Address

• Key idea: 31 30 12 11 10 9 8 3210

– Divide cache into sets 22 8

– Allow block anywhere in a set

• Advantages: Index
0
V Tag Data V Tag Data V Tag Data V Tag Data

1
– Better hit rate 2

• Disadvantage: 253
254
– More tag bits 255
22 32
– More hardware
– Higher access time

4-to-1 multiplexor

Hit Data

A Four-Way Set-Associative Cache

Fully Associative Cache Design
• Key idea: set size of one block
– 1 comparator required for each block
– No address decoding
– Practical only for small caches due to
hardware demands
tag in 11110111 data out 1111000011110000101011

= tag 00011100 data 0000111100001111111101

= tag 11110111 data 1111000011110000101011
= tag 11111110 data 0000000000001111111100
= tag 00000011 data 1110111100001110000001
= tag 11100110 data 1111111111111111111111
In-Class Exercise
• Given the following requirements for cache design for
a 32-bit-address computer: (1) cache contains 16KB
of data, and (2) each cache block contains 16 words.
(3) Placement policy is 4-way set-associative.
– What are the lengths (in bits) of the block offset
field and the index field in the address?

– What are the lengths (in bits) of the index field and
the tag field in the address if the placement is 1-
way set-associative?

CSCE 430/830, Memory

Hierarchy Introduction
Q3: Which block should be replaced on a miss?

• Easy for Direct Mapped

• Set Associative or Fully Associative:
– Random
– LRU (Least Recently Used)

Assoc: 2-way 4-way 8-way

Size LRU Ran LRU Ran LRU
Ran
16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.0%
64 KB 1.9% 2.0% 1.5% 1.7% 1.4% 1.5%
256 KB 1.15% 1.17% 1.13% 1.13% 1.12%
1.12%

CSCE 430/830, Memory

Hierarchy Introduction
Q3: After a cache read miss, if there are no empty
cache blocks, which block should be removed from
the cache?

The Least Recently Used

A randomly chosen block?
(LRU) block? Appealing,
Easy to implement, how
but hard to implement for high
well does it work?
associativity

Miss Rate for 2-way Set Associative Cache

Size Random LRU Also,
try
16 KB 5.7% 5.2% other
64 KB 2.0% 1.9% LRU
approx.
256 KB 1.17% 1.15%

CSCE 430/830, Memory

Hierarchy Introduction
 Reducing Cache Misses: 1. Larger Block Size

Using the principle of locality. The larger the block, the greater the chance parts
of it will be used again.

25% Size of Cache

20% 1K

4K
15%
Miss
16K
Rate
10%
64K
5% 256K

0%
16

32

64

128

256
Block Size (bytes)
CSCE 430/830, Memory
Hierarchy Introduction
Increasing Block Size
• One way to reduce the miss rate is to increase
the block size
– Take advantage of spatial locality
– Decreases compulsory misses
• However, larger blocks have disadvantages
– May increase the miss penalty (need to get more
data)
– May increase hit time (need to read more data from
cache and larger mux)
– May increase miss rate, since conflict misses
• Increasing the block size can help, but don’t
overdo it.

CSCE 430/830, Memory

Hierarchy Introduction
 Block Size vs. Cache Measures
Increasing Block Size generally increases
Miss Penalty and decreases Miss Rate
As the block size increases the AMAT starts
to decrease, but eventually increases
Hit Time + Miss Penalty X Miss = Avg. Memory Access Time
Rate

Block Size Block Size

Block Size
CSCE 430/830, Memory
Hierarchy Introduction
Reducing Cache Misses: 2. Higher Associativity

• Increasing associativity helps reduce conflict

misses
• 2:1 Cache Rule:
– The miss rate of a direct mapped cache of size N is
about equal to the miss rate of a 2-way set
associative cache of size N/2
– For example, the miss rate of a 32 Kbyte direct
mapped cache is about equal to the miss rate of a
16 Kbyte 2-way set associative cache
• Disadvantages of higher associativity
– Need to do large number of comparisons
– Need n-to-1 multiplexor for n-way set associative
– Could increase hit time
– Consume more power
CSCE 430/830, Memory
Hierarchy Introduction
AMAT vs. Associativity

Cache Size Associativity

(KB) 1-way 2-way 4-way 8-way
1 7.65 6.60 6.22 5.44
2 5.90 4.90 4.62 4.09
4 4.60 3.95 3.57 3.19
8 3.30 3.00 2.87 2.59
16 2.45 2.20 2.12 2.04
32 2.00 1.80 1.77 1.79
64 1.70 1.60 1.57 1.59
128 1.50 1.45 1.42 1.44
Red means A.M.A.T. not improved by more associativity
Does not take into account effect of slower clock on rest of program

CSCE 430/830, Memory

Hierarchy Introduction