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Subject Name: Fundamentals Of CMOS VLSI

Subject Code: 10EC56

Prepared By: Aswini N, Praphul M N

Department: ECE

Date: 10/11/2014

Engineered for Tomorrow

Prepared by : MN PRAPHUL & ASWINI N

Assistant professor
ECE Department

Date : 11/10/14
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Unit 2
Circuit design process
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Syllabus
MOS Layers.
Stick diagram.
Design rules and layout
Examples
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MOS layers

MOS circuits are formed on four basic layers:

 N-diffusion
 P-diffusion
 Polysilicon
 Metal

•These layers are isolated by one another by thick or thin silicon dioxide insulating
layers.
•Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel.
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Stick diagrams
• Stick diagrams may be used to convey layer information through the use
of a color code.
• For example:
 n-diffusion --green
 poly -- red
 blue -- metal
 yellow --implant
 black --contact areas
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Encodings for NMOS process:

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Encodings for CMOS process:

•Figure shows when a n-transistor is

formed: a transistor is formed when
a green line (n+ diffusion) crosses a
red line (poly) completely.

•Figure also shows when a p-

transistor is formed: a transistor is
formed when a yellow line(p+
diffusion) crosses a red line (poly)
completely
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Encoding for BJT and MOSFETs:

layers in an nMOS chip consists of

 a p-type substrate
 paths of n-type diffusion
 a thin layer of silicon dioxide
 paths of polycrystalline silicon
 a thick layer of silicon dioxide
 paths of metal (usually aluminium)
 a further thick layer of silicon dioxide
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nMOS depletion inverter diagrams

schematic stick diagram layout

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CMOS inverter diagrams

schematic stick diagram layout

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NAND gate implementation using nmos depletion

schematic stick diagram

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NOR gate implementation using nmos depletion

schematic stick diagram

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NAND gate implementation using CMOS

schematic stick diagram

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NOR gate implementation using CMOS

schematic stick diagram

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Lambda based Design Rules:

Design rules include width rules and spacing rules.

Mead and Conway developed a set of simplified scalable λ -based

design rules, which are valid for a range of fabrication technologies.

In these rules, the minimum feature size of a technology is

characterized as 2 λ .

 All width and spacing rules are specified in terms of the

parameter λ .
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Design rules for the diffusion layers and metal layers

Figure shows the design rule n diffusion, p diffusion, poly, metal1 and
metal 2. The n and p diffusion lines is having a minimum width of 2λ and
a minimum spacing of 3λ. Similarly it shows for other layers.
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Design rules for transistors and gate over hang

distance

Figure shows the design rule for the transistor, and it also shows
that the poly should extend for a minimum of 2λ beyond the
diffusion boundaries.(gate over hang distance)
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Via
VIA is used to connect higher level metals from metal1 connection.

Figure shows the design rules for contact cuts and Vias. The
design rule for contact is minimum 2λx2λ and same is applicable
for a Via.
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Buried contact and Butting contact

Buried Butting contact

contact is The layers are butted together in
made down such a way the two contact cuts
each layer to become contiguous
be joined
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CMOS LAMBDA BASED DESIGN RULES:

Figure shows the rules to be followed in CMOS well processes to accommodate

both n and p transistors
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BASIC PHYSICAL DESIGN FLOW

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SCHEMATIC AND LAYOUT OF BASIC GATES

a) CMOS INVERTER NOT GATE

Schematic Stick diagram Layout

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b) NAND GATE

Schematic Stick diagram Layout

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TRANSMISSION GATE

Symbol schematic stick diagram

layout