Neural Semiconductor Limited: Digital VLSI Testing Lecture-2 (Introduction)
Neural Semiconductor Limited: Digital VLSI Testing Lecture-2 (Introduction)
Lecture-2
(Introduction)
Design Verification
•System
• PCB
• VLSI
• PCB and VLSI having similar
kind of fabrication
• Possible defects
System Level Operation
• Reliability
• Normal Operation Probability,
• System Availability =
System Level Testing
• Online Testing
• Offline Testing
Test Generation
• Approaches to test:
• Functional Testing: Using all entries of truth table for the combinational
circuit.
• Reject rate =
Test Generation (Contd.)
• For example if a PCB has 40 chips, each with 90% fault coverage
and 90% yield, has a reject rate of 41.9%, almost 16-17 chips
will be rejected among the 40 chips.
• Fault Simulation
• Single Fault Model: Whole circuit has only 1 fault. #of faults = k X n
• Multiple Fault Model: Circuit can have more than 1 fault sites.
#of faults = (k + 1)n - 1
Fault Models
• Equivalent Faults
• Faults that have identical behaviour for all possible input patterns
• Only one from a set of equivalent faults need to be simulated
• Fault Collapsing
• Removing Equivalent Faults
• Except for the one to be simulated
• Reduces Total Number of Faults
• Reduces fault simulation time
• Reduces test pattern generation time
Reference
• Lecture Link:
https://www.youtube.com/watch?v=JnwoEXs8ezI
Thank You
[email protected]