Computer Architecture I: Digital Design

Dr. Robert D. Kent

Computer Architecture

Basic Computer Organization & Design

 Review
• We introduced registers

• We discussed the kinds of Transfer, Arithmetic,

Logic and Shift Microoperations
– Introduced a language that connects SSI to MSI
– Combined groups of instructions using multi-selection
circuits

• We discussed general aspects of CPU, Memory

and Bus architectures
 Considering the next problem in design

• A computer organization involves combining

everything we have learned to date into a single
integrated unit
– What is a computer?

• Von Neuman refers to a computer as a “stored

program digital computer”
– What is a program?
• What is an instruction?
• How are instructions executed?
 Goals
• We conclude our lecture series by considering
computer organization
– Combining the CPU, Memory and Bus architectures

• We introduce the concept of an instruction

– Instruction design and architecture
– Microoperation sequencing (timing, control)
– Roles of different registers

• We will follow a model of a virtual/logical computer

organization adapted from M. Mano (Computer
System Architecture, 3d Edition)
 Computer – High Level View

• CPU, Memory and Bus architectures with interface to I/O.

Data Bus
Volatile Memory (RAM) Input Output
M[0]
I/O Bus
M[1] CPU
Control
Mano Unit
Inputdefines
and (CU)is as 4096 words.
Output
Memory
defined using the
This requires ASCII busCLK
an Address of 12 bits
Control code of length 8 bits.
to act as selection inputs to
Bus address/data multiplexers.
M[K] Arithmetic and Logic
The fundamental unit of addressable
memoryUnit is the word. Each word is 16
(ALU)
bits long. The Data bus carries exactly
1 word of data between Memory and
CPU.

M[L-1] Address Bus

 The Mano model of the CPU Registers
• CPU registers used in the model (Mano), categorized by
length:

– PC :: Program counter (address – 12 bits)

– AR :: Address register (address – 12 bits)

– IR :: Instruction register (data – 16 bits)

– DR :: Data register (data – 16 bits)
– AC :: Accumulator (data – 16 bits)

– INR :: Input buffer register (ASCII data – 8 bits)

– OUTR :: Output buffer register (ASCII data – 8 bits)

– SCR :: Sequence counter register (4 bits)

– E, R :: Single bit flip-flops (flag/utility, interrupt)

 CPU Register Lengths
• The register lengths (number of flip-flops to store bits) are determined by
number of memory locations (address space) and the bus width (in bits)
that determines the number of bits transferred between Memory and
CPU, or between I/O channels and CPU.

PC 12 bits
AR
DR
16 bits
IR
AC
INR
8 bits
OUTR
SCR
4 bits
E
1 bit
R 1 bit
 Stored programs
• A stored program is a set of instructions and data
expressed in binary language, stored in non-volatile (ie.
disk storage) memory

• Programs can be executed only from Memory.

– Thus, a program must be loaded from disk to RAM in
order to execute it.
– Loaded programs are called processes.
– Individual instructions must be transferred to the CPU
where they are executed, using data that must be obtained
from either CPU registers or RAM

• A process is executed by executing each individual

instruction that, collectively, fulfill the intentions of the
programmer.
 Instruction Architecture
• The list of all instructions engineered for a computer’s CPU
is called the instruction set.
• To distinguish each instruction, they are assigned a unique
numeric code
– Can be done in many ways
– Does not need to be ordinal (ie. starting from 0 and
running contiguously)
– Can be partially ordinal and partially hierarchical
• Mano’s approach
• Instructions must be capable of referencing Memory and/or
CPU addresses in order to cause data to be transferred and
operated on.
 Instruction Architecture
• Instructions consist of
– Operation code data
– Address data
– Mode data
• Direct addressing – data found at the specified address
• Indirect addressing – data found at the address found at the
The number of memory referenced operands varies from computer
specified address (pointertoconcept)
computer.
0 Mano simplifies the instruction architecture to permit zero or one
1 memory address field. In the case of Indirect addressing mode
there are two memory accesses, but only one reference.

15 14 12 11 0
IR
Mode I OpCode Address
bit
 Instruction Hierarchy
• It is desirable to engineer the computer to support a
reasonable number of independent instructions
– Examples:
• Add, subtract, transfer, shift, logic, comparison, branch,
input, output
– 4 bits can be used to support 24 = 16 unique
instructions
• Leaves 12 bits to represent an address space of 4096 words
– However, 16 instructions is not enough for most
program needs
15 14 12 11 0
IR
I OpCode Address
 Instruction Hierarchy
• It is desirable to engineer the computer to support a
reasonable number of independent instructions
– Use a hierarchical scheme (1+3 scheme)
• OpCode – 3 bits – supports 8 unique codes
– 0-6 (instructions)
– 7 (toggle)
• Mode – 1 bit – supports 2 addressing modes
– I=0 Direct addressing
– I=1 Indirect addressing
• Special Case :: OpCode = 7 (toggle) PLUS Mode bit (I)
– Use 12 bits of Address field to specify additional instructions

15 14 12 11 0
IR
I OpCode Address
 Instruction Hierarchy
• Mano’s instruction set consists of 25 instructions:
Instruction

OpCode (0-6) OpCode (7)

Direct (I=0) Indirect (I=1) Direct (I=0) Indirect (I=1)

4 bit code 4 bit code 16 bit code 16 bit code

0 AND 8 AND 7800 CLA F800 INP
1 ADD 9 ADD 7400 CLE F400 OUT
2 LDA A LDA 7200 CMA F200 SKI
3 STA B STA 7100 CME F100 SKO
4 BUN C BUN 7080 CIR F080 ION
5 BSA D BSA 7040 CIL F040 IOF
6 ISZ E ISZ 7020 INC
7010 SPA
7008 SNA 6
7 7004 SZA
7002 SZE 12
7001 HLT
 Instruction Set Completeness
• Selection of instructions should span a variety of
applications suitable to support programming
An important issue for many applications is the
number of programmable (general purpose) registers.
– Arithmetic, logical
Mano adopts and shiftapproach
a minimalist instructions
providing a single
such register, the accumulator AC.
– Instructions for moving
This simple data
case does tofull
allow andillustration
from memory
of all and CPU
registers computational requirements of a more powerful
computer with a larger instruction set (but with much
added cost to programming).
– Program control instructions,
Among commercial instructions
computers one findsthat
both check status
complex (large number) instruction sets (CISC) and
conditions
reduced (number) instruction sets (RISC).

– Input and Output instructions

 Instruction Processing & Instruction Cycle
• Instruction processing cannot occur in a single clock
cycle – it is too complicated !
– Must fetch the instruction from memory and load the
instruction register, IR.
– Must decode the Operation Code to determine whether data
must be fetched and whether we fetch data directly, or
indirectly
– Must fetch required data, if any, from memory into CPU
• OR, must store data from CPU into memory
• OR, must obtain data from Input
• OR, must place data for Output
– Must process the data according to instruction logic
• Thus, the instruction cycle consists of a controlled
sequence of microoperations
 Timing and Control
• In order to control the steps of the instruction cycle, it is necessary to
introduce a counter, whose output is used as input to the control logic

– We will utilize a Sequence Counter Register (SC, or SCR). This is a register that
holds a count value, can be reset to zero and can be incremented (or
decremented) by one

CLR
– Each instruction will require a specified
SC number of time steps to complete a
sequence of microoperations. Each step of the sequenceINCis marked by a count
value in SC.
……
 Timing and Control
• The SC outputs a string of bits whose value is in the range from
0 to 2L-1
– Eg. for L=3, from 0 to 7
• We need a way of converting the bit string value to single bit
valued outputs labelled T0, T1, T2, T3, and so on, up to Tx
(where x = 2L-1)
• A decoder serves our purpose, recalling that the output from the
DEC is a 1 only on one line (the rest are 0`s)

Tx T2 T1 T0
….. CLR
SC INC
L-to-2 DEC
L

……
…
 Timing and Control
• Step 1: Where do we fetch the next instruction from
at T0 (start time)?

– The Program Counter register (PC) is assumed to hold the

address of the next instruction to be executed.
• It is loaded initially during the machine bootstrapping process.

– The PC is transferred to the Address Register (AR) which is

connected to the Address Bus Multiplexer.
• The AR provides the selection input to the address bus multiplexer to
enable RAM-CPU data transfers

PC
T0 : AR = PC Load

AR
 Timing and Control
• Step 2: How do weMemory
obtain the instruction from
Note how the PC is updated in parallel.

memoryThisat assumes that the next instruction (yet to be executed)

T1?sequence
in logical
Data bus
is actually located at the nextINC
memory
– The data storedM[AR] location.
DR address PCtransferred onto the
at the selected LD is

Data This restriction

Busincluding
and then toto
non-sequential
the Data instructions
Register is removed
(DR) in byCPU.
the
instructions that modify the PC explicitly.
– The instruction data is transferred IR LD
immediately to the
Instruction Register (IR) CPU bus
AR LD
Address bus
T1 : DR = M[AR] , IR = DR , PC = PC + 1

NOTE: Mano does not include this step explicitly.

However, in most systems the initial transfer from memory is always to a CPU
buffer, such as DR. In effect, this is simply a pipeline element of a transfer circuit
that adds an intermediate parallel load through DR to IR.
This can be modified to act as a Master-Slave element which is necessary to build
a Direct Memory Access (DMA) control circuit.
 Timing and Control
• Step 3: How do we decode the instruction intention (ie.
meaning, operational
NOTE: definition) at T2?
–AllThe
instructions share the steps T0,
OpCode, Mode and Address field bits all serve as inputs
T1 and T2.
to the Control Logic Gates that select the specific instruction
However, depending on what each
semantics
specific instruction requires, the
• Direct
control addressing
logic for higher time steps is
more complicated,
• Indirect requiring more
addressing Note the reference to a
inputs. DECoder unit to explicitly
• CPU register addressing access the IR bits indicated
• Input
• Output

T2 : {D0,...,D7} = DEC( IR(12-14) ),

AR = IR(0-11), The AR may be directly
connected to the IR
I = IR(15) address bits indicated
 Timing and Control
• The instruction cycle consists of a controlled sequence of
microoperations using control logic gates and a sequence counter.
I OpCode Address
IR 15 14 13 12 11 0

Connect it all
2 1 0 together !
3x8 DEC Enable one
specific logic
7 6 5 4 3 2 1 0 circuit Signal the SC to
advance (INC) to
next timing
Control
value, or reset.
Control
Logic
Outputs
Timing inputs Gates
F E D C B A 9 ... 1 0
4x16 DEC
Clock has
3 2 1 0
4-bit
not been
INC included!
Sequence
Counter (SC) CLR
 An Architectural Basis for Programming

• Programs are written by humans and typically use high-level languages to

express logic.
– Programmers learn to use languages based on expressiveness and ease of
use
– Language designers are not limited by imagination in developing new
operations and techniques
– But, too much complexity presents real difficulties for practical,
widespread usage.

• Computer Instruction Sets are limited by the complexities of

– Working with materials on a micro- and nano-scale of fabrication
– Understanding of fundamental physics applied to signaling and
electromagnetic properties of matter
– Optimal design of complicated circuits with well-posed input/output logics
– Power efficiency issues, temperature control
– Performance and timing considerations
– Many other practical and theoretical objectives
 An Architectural Basis for Programming

• Thus, Instruction Sets are minimal reflections (subduced

mappings) of high-level operation and function sets
– Limited number of hardware operations
• Assignment = Transfer
• Integer arithmetic (may include optimized floating point)
• Logic, Shift
• Non-sequential control (branching for decision and repetition)
• Input and Output
• Communications
• Specialized operations (string, array)
• Specialized addressing modes
• Enhanced data and register access modes
 Instruction Categories
• Instructions may be placed in several different kinds of categories
– Conceptual application, or meaning
– Performance based on location of operation
• Studies of application programs have found that most programs perform best
when optimized for use of the CPU (called CPU intensive jobs)
• However, many programs must interact with peripheral devices that operate on
relatively slow electromechanical hardware (called I/O intensive jobs)
• Typically, programs are hybrids that must access I/O, memory and CPU in
various combinations and for different intervals of intensive use of a particular
resource.

• We adopt a performance based on location categorization of

instructions
– Register reference
– Memory reference
– I/O reference

– Within each category above we define conceptual subcategories

 Register Reference Instructions
• Referencing CPU registers for data processing is the
fastest data access possible

– We consider two registers

• The Accumulator (AC)

– Used for arithmetic, logic and shift AC
– Also used for input and output

• The E-bit (E) utility flip-flop E

– Used in shift operations
– May be used in arithmetic operations

15 14 12 11 0
IR 0 1 1 1 Operation control bits
 Register Reference Instructions
• The complete set of all instructions defined by Mano
– Mnemonic means a string that suggests the meaning.
Hex Mnemonic Binary coding Meaning
7800 CLA 0111100000000000 CLear Accumulator
7400 CLE 0111010000000000 CLear E
7200 CMA 0111001000000000 CoMplement Accumulator
7100 CME 0111000100000000 CoMplement E
7080 CIR 0111000010000000 CIrcular shift Right
7040 CIL 0111000001000000 CIrcular shift Left

7020 INC 0111000000100000 INCrement AC

7010 SPA 0111000000010000 Skip if Positive Accumulator

7008 SNA 0111000000001000 Skip if Negative Accumulator
7004 SZA 0111000000000100 Skip if Zero Accumulator
7002 SZE 0111000000000010 Skip if Zero E

7001 HLT 0111000000000001 HaLT the computer

 Register Reference Instructions
• Within this instruction subset, one may find it
convenient to group the instructions by which register is
affected
Hex Mnemonic
7800 CLA
7200 CMA
7080 CIR
AC affected
7040 CIL
7020 INC
7010 SPA
7008 SNA
7004 SZA

7400 CLE E affected

7100 CME
7002 SZE

7001 HLT Control affected

 Register Reference Instructions
• Clear, Complement or Increment : AC register.

CLA
Hex Mnemonic RTL CMA
INC
7800 CLA AC = 0
7200 CMA AC = ~ AC AC
7020 INC AC = AC + 1

• Clear, Complement : E register

CLE
CME
Hex Mnemonic RTL
7400 CLE E = 0 E
7100 CME E = ~ E
 Register Reference Instructions
• Shift AC register.
– This is a circular shift that is performed using the E register
– Control over timing ensures all operations operate in parallel
• Eg. Use master-slave flip-flops in registers

Hex Mnemonic RTL

7080 CIR AC(0-14) = AC(1-15),
AC(15) = E, E = AC(0)

7040 CIL AC(1-15) = AC(0-14),

AC(0) = E, E = AC(15)

AC
 Register Reference Instructions
• Skip on <condition> : AC register.
– Tests sign/value status of 2’s complement integer in AC
– If status matches query, advance PC by one instruction word

Hex Mnemonic RTL

7010 SPA ( AC > 0 ) : PC = PC + 1
7008 SNA ( AC < 0 ) : PC = PC + 1
7004 SZA ( AC = 0 ) : PC = PC + 1

• Skip on Zero condition : E register

– Test status of E bit. If not zero, proceed to the next instruction.
– If zero, advance PC by one instruction word (recall that it has
already been incremented by one, so this causes skipping the next
instruction in contiguous sequence.

Hex Mnemonic RTL

7002 SZE ~ E : PC = PC + 1
 Register Reference Instructions
• Halting the computer
– Disable all circuits (over-ride all specific Enable controls with a
general Disable).

Hex Mnemonic RTL

7001 HLT Disable all circuits

• Bootstrapping the computer

– “Turning on” the computer simply refers to supplying electricity to the
circuits and to the clock
– Since no instruction may be fetched to IR for execution unless a RAM
address is specified for the instruction, it is necessary to explicitly load
the PC with an initial instruction address.
– The textbook does not discuss this matter very much. To state it
briefly, a special memory called a ROM (a non-volatile memory
device) contains a sequence of instructions that loads an operating
system program, from disk into memory, and with the PC set to an
initial instruction address.
 Memory Reference Instructions
• Once an instruction has been loaded to IR, it may require further
access to memory to perform its intended function
– Direct Access – access the storage at the specified IR address
– Indirect Access – first, transfer to DR the data stored at the
specified IR address, then (after
transferring DR to AR), access Operation Codes
this fetched address to perform Direct Indirect
the required function. I=0 I=1 Mnemonic

0 8 AND
1 9 ADD
2 A LDA
3 B STA
4 C BUN
5 D BSA
6 E ISZ
15 14 12 11 0
IR I OpCode Memory Address
 Memory Reference Instructions
• Direct access mode (I=0) operation semantics
Operation Codes The actual number of timing steps (Tk) may vary
from 1 to 2 (or even 3) steps, depending on how the
Direct control timing circuits are designed.
I=0 Mnemonic RTL
0 AND DR = M[AR] ; AC = AC ^ DR
1 ADD DR = M[AR] ; AC = AC + DR
2 LDA DR = M[AR] ; AC = DR
3 STA DR = AC ; M[AR] = DR

4 BUN AR = IR(0-11) ;
PC = AR
5 BSA AR = IR(0-11) ;
M[AR] = PC , PC = AR + 1
6 ISZ AR = IR(0-11) ; DR = M[AR] ;
AC = DR ; AC = AC + 1 ; DR = AC ;
M[AR] = DR , (AC=0) : PC = PC + 1
 Memory Reference Instructions
• Indirect access mode (I=1) operation semantics using
AND and ADD
– First, fetch the pointer (address) data from memory to
obtain the indirect reference
– Second, fetch the needed data from the just-fetched address
The actual number of timing steps (Tk) may vary
Operation Codes from 2 to 3 steps, depending on how the control
timing circuits are designed.
Indirect
I=1 Mnemonic RTL
8 AND AR = IR(0-11) ; DR = M[AR]
AR = DR(0-11) ; DR = M[AR]
AC = AC ^ DR
9 ADD AR = IR(0-11) ; DR = M[AR]
AR = DR(0-11) ; DR = M[AR]
AC = AC + DR
 Memory Reference Instructions
• Transfer instructions
– Copy data to or from memory and CPU
• Loading (fetching) refers to memory-to-CPU transfers
• Storing refers to CPU-to-memory transfers

Operation Codes
Direct Indirect
I=0 I=1 Mnemonic RTL
2 A LDA DR = M[AR] ; AC = DR
3 B STA DR = AC ; M[AR] = DR

M
Data DR AC

Address bus
AR
MUX
 Memory Reference Instructions
• ADDition, Logical AND instructions
– Logical AND is done on all bits in parallel
– Numeric (2’s complement) addition may be done in serial,
or in parallel using Look-Ahead circuits
Operation Codes
Direct Indirect
I=0 I=1 Mnemonic RTL
0 8 AND DR = M[AR] ; AC = AC ^ DR
1 9 ADD DR = M[AR] ; AC = AC + DR

M
Data DR AC

Address bus
AR
MUX ADD/AND Logic
 Memory Reference Instructions
• Branching
– Instructions that explicitly modify the PC during execution
– This implies that the next instruction to be executed is not located in
the next contiguous word of storage.
– Used to program IF-THEN-ELSE (Decision control) and WHILE-DO
(Repetition control) constructs in high-level languages.
(a) BEFORE COMPLETION OF (b) AFTER COMPLETION
EXECUTION (after DECoding) OF EXECUTION
M M

PC Next instr. PC Next instr.

Current instr. This is called a Current instr.

Branch Point
Address
 Memory Reference Instructions
• Timing and control logic must be carefully worked out for all
steps in the instruction.
– For example, using the AND instruction:

T0: AR = PC, SC = SC + 1
T1: IR = M[AR], PC = PC +1, SC = SC +1
T2: {D0..D7} = DEC(IR(12..14)), AR = IR(0..11), I = IR(15), SC = SC+1
D0.T3: DR = M[AR], SC = SC+1
I’.D0.T4: AC = AC^DR, SC = 0
I.D0.T4: AR = DR(0..11), SC = SC+1
I.D0.T5: DR = M[AR], SC = SC+1
I.D0.T6: AC = AC^DR, SC = 0

– Note how the Direct and Indirect forms of the instruction are
differentiated using the I (or I’) bit value for control differentiation.
 Memory Reference Instructions
• Branch UNconditional instruction
– I = 0 :: Replace PC by address in IR(0-11)
– I = 1 :: Replace PC by the address found at the address in IR(0-11)
• That is :: PC = M[ M[ IR(0-11) ] ]

Operation Codes
Direct Indirect
I=0 I=1 Mnemonic RTL
4 C BUN AR = IR(0-11)
PC = AR

PC
IR
I=1 I=0
M
Data DR

Address bus
AR
MUX
 Memory Reference Instructions
• Branch and SAve instruction
– Used for programming subroutine calls
Operation Codes
Direct Indirect
I=0 I=1 Mnemonic RTL
5 D BSA AR = IR(0-11)
M[AR] = PC , PC = AR + 1

(a) BEFORE SUBROUTINE CALL (b) AFTER SUBROUTINE CALL

M M

PC Subr. call instr. PC Subr. call instr.

Return addr.
Subr. entry instr. Subr. entry instr.
 Memory Reference Instructions
• Increment and Skip if Zero instruction
– Used to implement a counter based <do-while> construct
I=0 I=1 Mnemonic RTL
6 E ISZ AR = IR(0-11) , DR = M[AR]
AC = DR , AC = AC + 1 , DR = AC
M[AR] = DR , (AC=0) : PC = PC + 1

(a) BEFORE (b) AFTER

M M

PC Current instr. PC < 0 Current instr.

Branch instr. Branch instr.

Continue instr. Continue instr.

=0
AR AR
Data value Data value + 1
Input, Output and Interrupt Instructions

15 14 12 11 0
IR 1 1 1 1 I/O operation control bits
 Input/Output Instructions
• Used for communicating data between CPU and I/O peripheral
devices
• Also, need instructions to support programmed polling.
– Polling refers to waiting for a condition to be true before proceeding

16 bit
OpCode Mnemonic Meaning
F800 INP Input ASCII char
F400 OUT Output ASCII char
F200 SKI Skip if input flag (FGI=1)
F100 SKO Skip if output flag (FGO=1)

F 8
4
2
1
15 14 12 11 0
IR 1 1 1 1 I/O operation control bits
 Input/Output Instructions
• Each peripheral device has a communications and control
interface that interacts with the computer’s interface logic circuits
– Input
• Need a data buffer (INPR) and a flag (FGI) indicating buffer empty/full
– Output
• Need a data buffer (OUTR) and a flag (FGO) indicating buffer empty/full

FGO
Status
Printer Receiver
Interface OUTR Data

NOTE:
AC(H) AC(L) Only the low order part
of AC is used.

Keyboard Transmitter INPR Data

Interface
Status
FGI
PERIPHERAL DEVICES CPU
 Interrupts
• Input and Output interactions with electromechanical peripheral
devices require huge processing times compared with CPU
processing times
– I/O (milliseconds) versus CPU (nano/micro-seconds)
• Interrupts permit other CPU instructions to execute while waiting
for I/O to complete
– Need an additional 1-bit IEN flip-flop to store the interrupt status (0/1)

16 bit
OpCode Mnemonic Meaning
F080 ION Interrupt Enabled (IEN  1)
IEN
F040 IOF Interrupt Disabled (IEN  0)

15 14 12 11 0
IR 1 1 1 1 I/O operation control bits
 Interrupts
• In this approach, interrupts are used only with I/O handling
– In addition to a flip-flop to store the Interrupt Enable state, one more
flip-flop (R) is needed to store the I/O Status (Ready/Not_ready).
– In general, interrupts may be used with arbitrary instructions for
exception trapping and handling
1-bit registers
We will also
require one final =0
IEN IEN
register, called TR All of these
(for transfer). This =1 flipflops are
can be 16 bits, but assumed to be
must be at least 12 =1 FGI
FGI reset to 0 when
bits. bootstrapping the
=0 computer.
=1 FGO
FG0

=0
R1 R
Control Bus
 Interrupt Handling Flowchart

Instruction Cycle =0 =1 Interrupt Cycle

R

Fetch/Decode Instruction
Store return address
in location 0
M[0]  PC IEN
Execute =0
IEN
Instruction
=1 FGI
=1 Branch to location 1
FGI PC  1

=0 FGO
=1
FG0 Reset Interrupt, Ready
IEN  0 R
=0 R0
R1
TR
Control Bus
 Interrupt Handling Flowchart

: AR  0 , TR  PC \\ NOTE TRANSFER REG.

R T0 Memory Memory
=1
R
R 0T1 : M[AR]  TR , PC  0 0 256
Interrupt Cycle
PC 
R 1T2 0: BUN PC + 1 , IEN  0 , R  0 , SC  0 PC=1
1120 0 BUN 1120

Store return address

in location 0
Main Prog. Main Prog.
M[0]  PC

255 Curr Instr. 255 Curr Instr.

PC=256 Next Instr. 256 Next Instr.
Branch to location 1
PC  1

1120 I/O Program 1120 I/O Program

Reset Interrupt, Ready
IEN  0
1 BUN 0 R0 1 BUN 0

(a) BEFORE (b) AFTER

Interrupt Interrupt
 Control Logic
• Timing of microoperations requires explicit enabling of
logic circuits through the Control Unit logic gates
 Timing and Control - Revisited
• The instruction cycle consists of a controlled sequence of
microoperations using control logic gates and a sequence counter.
I OpCode Address
IR 15 14 13 12 11 0

2 1 0
3x8 DEC
7 6 5 4 3 2 1 0

Control
Control
Logic
Outputs
Gates
F E D C B A 9 ... 1 0
4x16 DEC
3 2 1 0
4-bit INC
Sequence
Counter (SC) CLR
 Control Logic
• Timing of microoperations requires explicit enabling of
logic circuits through the Control Unit logic gates

• Need signals …

– to control the inputs of the 9 registers

– to control the read and write inputs of memory
– to set, clear or complement the flip-flops
– for Selector inputs to select a register for the bus
– to control the AC adder, logic and shift circuit
 Control Logic – Example: AR
• Consider all instructions that modify the AR register
• Construct an AR control circuit
D7’ Condition Microoperation
I R’ T0 : AR  PC
T3
R’ T2 : AR  IR(0-11)

T2 D7’ I T3 : AR  M[AR]
R T0 : AR  0
D5 T4 : AR  AR + 1
R
T0
LD
D5 INC
AR
T4
CLR
Clk

To From
Bus Bus
 Control Logic
• In previous lectures we discussed complex register
circuits
– Control was exerted through enabling inputs
• The textbook provides additional examples of
controlling logic circuits
– Control of single flip-flops
– Control of common bus
• All registers can be adapted to controls
• Indeed, all computer circuits can be adapted to controls
– Using enable inputs
– Using control circuits
– Using counters, and so on.
 Representing a Complete Architecture
• Small Scale Integration
– Logic Gates
– Simple Circuits – Combinational & Sequential

• Medium Scale Integration

– Functional Circuits and Control Logic
– Arithmetic, Logic, Shift, Comparison
– Decoders
– Multiplexers

• Large Scale Integration

– CPU
• Instruction set – Arithmetic & Logic Unit Subsystem
• Control logic – Control Unit Subsystem
• Registers
– Memory
• Memory storage cells
• Address, Data and Control Bus structure
– Input-Output
• Buffer registers, Control
 Representing a Complete Architecture
• Hardware
– CPU
• Instruction set – Arithmetic & Logic Unit Subsystem
• Control logic – Control Unit Subsystem
• Registers
– Memory Memory
• Memory storage cells 4096 words
• Address, Data and Control Bus structure
– Input-Output, Bus Network 16 bits/word
• Buses, Buffer registers, Control

CPU Buses
9 Registers Address
- AR, PC, DR, AC, IR, TR, OUTR, INPR, SC
Data
7 Flip-flops
- I, S, E, R, IEN, FGI, FGO Control

2 Decoders Buffer connections

- 3x8 Operation DEC, 4x16 Timing DEC
Control logic, ALU circuits
 Summary
• We adopted and discussed M. Mano’s logical model of computer
architecture.

• Instruction Set
• Control architecture
• Instruction processing
– Register access
– Memory access (Direct, Indirect)
– I/O access
– Interrupts
• Timing sequences of micro-operations

• In the final sequence of lectures slides we discuss some issues related

to programming
– Assembly language
– Assembler translators
– Programming examples