Hawassa University, Institute of Technology School of Electrical and

Computer Engineering

Embedded Systems (ECEg-5702)

Lecture 3: PIC18F Series

By Demisew T. 06/30/2021 1
Outline of the Lecture

Introduction

●
Program memory organization
●
Data memory organization
●
The configuration registers
●
The power supply
●
The reset
●
The clock sources
●
Watchdog timers
●
Capture/compare/PWM modules (CCP)
●
Analog-to-Digital Converter (A/D) Module
●
Interrupts

PIC18F452 Architecture:

Summary

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 2
Introduction

• Microchip Inc. has developed the PIC18 series of

microcontrollers for use in high-pin count, high-density, and
complex applications.
• The PIC18F microcontrollers offer cost efficient solutions for
general purpose applications written in C that
• use a real-time operating system (RTOS) and
• require a complex communication protocol stack such as TCP/IP, CAN, USB, or
ZigBee.
• PIC18F devices provide flash program memory in sizes from 8 to
128Kbytes and data memory from 256 to 4Kbytes, operating at a
range of 2.0 to 5.0 volts, at speeds from DC to 40MHz.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 3
Introduction

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 4
PIC18F452 Architecture

• The pin
configuratio
n of the
PIC18F452
microcontrol
ler (DIP
package) is
shown
below

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 5
PIC18Fxx2 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 6
PIC18F452 Architecture

Program Memory Organization

●
All PIC18F devices have a 21-bit program counter and hence are capable of addressing 2Mbytes of memory space.
●
User memory space on the PIC18F452 microcontroller is 0x00000 to 0x7FFF.
●
Accessing a nonexistent memory location (0x8000 to 0x1FFFFF) will cause a read of all 0s.
●
The reset vector, where the program starts after a reset, is at address 0000. Addresses 0x0008 and 0x0018 are
reserved for the vectors of high-priority and low-priority interrupts respectively, and interrupt service routines
must be written to start at one of these locations.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 7
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 8
PIC18F452 Architecture

Data memory organization

●
The data memory address bus is 12 bits with the capability to address up to 4Kbytes.
●
The memory in general consists of sixteen banks, each of 256 bytes, where only 6 banks are used.
●
The PIC18F452 has 1536 bytes of data memory (6 banks 256 bytes each) occupying the lower end of the data memory.
●
The special function register (SFR) occupies the upper half of the top memory bank.
●
SFR contains registers which control operations such as peripheral devices, timers/ counters, A/D converter, interrupts,
and USART.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 9
 PIC18F452 Architecture

Figure: The
PIC18F452 data
memory map

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 10
 PIC18F452 Architecture

Figure: The
PIC18F452 SFR
registers

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 11
PIC18F452 Architecture

The Configuration Registers:

●
PIC18F452 microcontrollers have a set of configuration registers.
●
Configuration registers are programmed during the programming of the flash
program memory by the programming device.
●
These registers and their Descriptions are given in the following Tables.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 12
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 13
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 14
PIC18F452 Architecture

CONFIG1H

●
The CONFIG1H configuration register is at address 300001H and is used to select the microcontroller clock sources. The
bit patterns are shown in Figure below

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 15
PIC18F452 Architecture

CONFIG2L

●
The CONFIG2L configuration register is at address 300002H and is used to select the brown-out voltage bits. The bit
patterns are shown in Figure below.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 16
PIC18F452 Architecture

CONFIG2H

●
The CONFIG2H configuration register is at address 300003H and is used to select the watchdog operations. The bit
patterns are shown in Figure below.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 17
PIC18F452 Architecture

The Power Supply:

●
PIC18F452 can operate with a supply voltage of 4.2V to 5.5V at the full speed of 40MHz.
●
The lower power version, PIC18LF452, can operate from 2.0 to 5.5 volts.
●
At lower voltages the maximum clock frequency is 4MHz, which rises to 40MHz at 4.2V.
●
The RAM data retention voltage is specified as 1.5V and will be lost if the power supply voltage is lowered below this
value.
●
In practice, most microcontroller-based systems are operated with a single +5V supply derived from a suitable voltage
regulator.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 18
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 19
PIC18F452 Architecture

The Reset:

●
Resetting a PIC18F microcontroller starts execution of the program from address 0000H of the program memory.
●
The microcontroller can be reset during one of the following operations:
●
Power-on reset (POR)
●
MCLR reset
●
Watchdog timer (WDT) reset
●
Brown-out reset (BOR)
●
Reset instruction
●
Stack full reset
●
Stack underflow reset
●
Two types of resets are commonly used: power-on reset and external reset using the MCLR pin.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 20
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 21
PIC18F452 Architecture

The Clock Sources:

●
The PIC18F452 microcontroller can be operated from an external crystal or ceramic resonator
connected to the microcontroller’s OSC1 and OSC2 pins.
●
In addition, an external resistor and capacitor, an external clock source, and in some models internal
oscillators can be used to provide clock pulses to the microcontroller.
●
There are eight clock sources on the PIC18F452 microcontroller, selected by the configuration register
CONFIG1H.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 22
PIC18F452 Architecture

The Clock Sources:

●
These are:
●
Low-power crystal (LP)
●
Crystal or ceramic resonator (XT)
●
High-speed crystal or ceramic resonator (HS)
●
High-speed crystal or ceramic resonator with PLL (HSPLL)
●
External clock with FOSC/4 on OSC2 (EC)
●
External clock with I/O on OSC2 (port RA6) (ECIO)
●
External resistor/capacitor with FOSC/4 output on OSC2 (RC)
●
External resistor/capacitor with I/O on OSC2 (port RA6) (RCIO)

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 23
PIC18F452 Architecture

The Clock Sources:

●
Crystal or Ceramic Resonator Operation:
●
For applications where accuracy of timing is important, a crystal should be used.
●
If a crystal is used, a parallel resonant crystal must be chosen, since series resonant crystals do not oscillate when the
system is first powered.
●
Figure in the next slide shows how a crystal is connected to the microcontroller. The capacitor values depend on the
mode of the crystal and the selected frequency.
●
Higher capacitance increases the oscillator stability but also increases the start-up time.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 24
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 25
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 26
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 27
PIC18F452 Architecture
• In the many applications where accurate timing is not required we can use
an external resistor and a capacitor to provide clock pulses.
• A close approximation of the clock frequency is 1/(4.2RC), where R should be
between 3K and 100K and C should be greater than 20pF.
• The oscillator frequency divided by 4 (FOSC/4) is available on pin OSC2 of
the microcontroller.
RCIO mode is similar to RC mode, except that the OSC2 pin can be used as a
general purpose digital I/O pin.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 28
PIC18F452 Architecture

Crystal or Resonator with PLL

●
One of the problems with using high-frequency crystals or resonators is electromagnetic interference.
●
A Phase Locked Loop (PLL) circuit is provided that can be enabled to multiply the clock frequency by 4.
●
Thus, for a crystal clock frequency of 10MHz, the internal operation frequency will be multiplied to 40MHz.
●
The PLL mode is enabled when the oscillator configuration bits are programmed for HS mode.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 29
PIC18F452 Architecture

Watchdog Timer

●
In PIC18F-series microcontrollers family members the watchdog timer (WDT) is a free running on-chip RC-based oscillator and does not
require any external components.
●
When the WDT times out, a device RESET is generated. If the device is in SLEEP mode, the WDT time-out will wake it up and continue with
normal operation.
●
The watchdog is enabled/disabled by bit SWDTEN of register WDTCON. Setting SWDTEN = 1 enables the WDT, and clearing this bit turns off
the WDT.
●
On the PIC18F452 microcontroller an 8-bit post scaler is used to multiply the basic time-out period from 1 to 128 in powers of 2.
●
The postscaler is controlled from configuration register CONFIG2H. The typical basic WDT time-out period is 18ms for a postscaler value of 1.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 30
PIC18F452 Architecture

Parallel I/O Ports:

●
The pins of a port are labeled as RPn, where P is the port letter and n is the port bit number. For example, PORTA pins are
labeled RA0 to RA7, PORTB pins are labeled RB0 to RB7, and so on.
●
When working with a port we may want to:
●
Set port direction
●
Set an output value
●
Read an input value
●
Set an output value and then read back the output value
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 31
PIC18F452 Architecture

PORTA:

●
In the PIC18F452 microcontroller PORTA is 7 bits wide and port pins are shared with other functions.
●
There are three registers associated with PORTA:
●
Port data register—PORTA
●
Port direction register—TRISA
●
Port latch register—LATA

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 32
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 33
PIC18F452 Architecture

PORTA:

●
PORTA is the name of the port data register.
●
The TRISA register defines the direction of PORTA pins, where a logic 1 in a bit position defines the pin as an input pin,
and a 0 in a bit position defines it as an output pin.
●
LATA is the output latch register which shares the same data latch as PORTA. Writing to one is equivalent to writing to
the other.
●
But, while reading from LATA, the value held in the PORTA/LATA data latch is transferred to the data bus independent of
the state of the actual output pin of the microcontroller.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 34
PIC18F452 Architecture

PORTA:

●
Bits 0 through 3 and 5 of PORTA are also used as analog inputs. After a device reset, these pins are programmed as
analog inputs and RA4 and RA6 are configured as digital inputs.
●
To program the analog inputs as digital I/O, the ADCON1 register (A/D register) must be programmed accordingly.
Writing 7 to ADCON1 configures all PORTA pins as digital I/O.
●
The RA4 pin is multiplexed with the Timer 0 clock input (T0CKI). This is a Schmitt trigger input and an open drain output.
●
RA6 can be used as a general purpose I/O pin, as the OSC2 clock input, or as a clock output providing FOSC/4 clock
pulses.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 35
PIC18F452 Architecture

PORTB:

●
In PIC18F452 microcontroller PORTB is an 8-bit bidirectional port shared with interrupt pins and serial device programming pins
●
PORTB is controlled by three registers:
●
Port data register—PORTB
●
Port direction register—TRISB
●
Port latch register—LATB
●
Each PORTB pin has a weak internal pull-up which can be enabled by clearing bit RBPU of register INTCON2.
●
These pull-ups are disabled on a power-on reset and when the port pin is configured as an output. On a power-on reset, PORTB pins are configured as digital inputs.
●
Internal pull-ups allow input devices such as switches to be connected to PORTB pins without the use of external pull-up resistors. This saves costs because the
component count and wiring requirements are reduced.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 36
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 37
PIC18F452 Architecture

PORTC, PORTD, PORTE, and Beyond

●
In addition to PORTA and PORTB, the PIC18F452 has 8-bit bidirectional ports PORTC and PORTD, and 3-bit PORTE.
●
Each port has its own data register (e.g., PORTC), data direction register (e.g., TRISC), and data latch register (e.g., LATC). The general
●
operation of these ports is similar to that of PORTA.2.1.
●
In the PIC18F452 microcontroller PORTC is multiplexed with several peripheral
●
functions as shown in Table 2.8. On a power-on reset, PORTC pins are configured as
●
digital inputs.
●
In the PIC18F452 microcontroller, PORTD has Schmitt trigger input buffers. On a
●
power-on reset, PORTD is configured as digital input. PORTD can be configured as an
●
8-bit parallel slave port (i.e., a microprocessor port) by setting bit 4 of the TRISE
●
register. Table 2.9 shows functions of PORTD pins.
●
In the PIC18F452 microcontroller, PORTE is only 3 bits wide. As shown in Table 2.10,
●
port pins are shared with analog inputs and with parallel slave port read/write control
●
bits. On a power-on reset, PORTE pins are configured as analog inputs and register
●
ADCON1 must be programmed to change these pins to digital I/O.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 38
PIC18F452 Architecture

PORTC, PORTD, PORTE, and Beyond

●
In addition to PORTA and PORTB, the PIC18F452 has 8-bit bidirectional ports PORTC and PORTD, and 3-bit PORTE.
●
Each port has its own data register (e.g., PORTC), data direction register (e.g., TRISC), and data latch register (e.g., LATC).
●
PORTC is multiplexed with several peripheral functions. On a power-on reset, PORTC pins are configured as digital inputs.
●
PORTD has Schmitt trigger input buffers. On a power-on reset, PORTD is configured as digital input. PORTD can be configured as an 8-
bit parallel slave port (i.e., a microprocessor port) by setting bit 4 of the TRISE register.
●
PORTE is only 3 bits wide port pins are shared with analog inputs and with parallel slave port read/write control bits. On a power-on
reset, PORTE pins are configured as analog inputs and register ADCON1 must be programmed to change these pins to digital I/O.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 39
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 40
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 41
PIC18F452 Architecture

Timers:

●
The PIC18F452 microcontroller has four programmable timers which can be used in many tasks, such
as
●
generating timing signals,
●
causing interrupts to be generated at specific time intervals,
●
measuring frequency and time intervals,
●
and so on.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 42
PIC18F452 Architecture

Timer 0:

●
Timer 0 has the following basic features:
●
8-bit or 16-bit operation
●
8-bit programmable prescaler
●
External or internal clock source
●
Interrupt generation on overflow
●
Timer 0 control register is T0CON.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 43
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 44
PIC18F452 Architecture

Timer 0:

●
The following operations are normally carried out in a timer application:
●
Clear T0CS to select clock FOSC/4
●
Use bits T0PS2:T0PS0 to select a suitable prescaler value
●
Clear PSA to select the prescaler
●
Load timer register TMR0L
●
Optionally enable Timer 0 interrupts
●
The timer counts up and an interrupt is generated when the timer value overflows from FFH to 00H in 8-bit mode (or from FFFFH to
0000H in 16-bit mode)

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 45
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 46
PIC18F452 Architecture

Timer 0:
• By loading a value into the TMR0 register we can control the count until
an overflow occurs.
• The formula that follows can be used to calculate the time it will take for
the timer to overflow (or to generate an interrupt) given the oscillator
period, the value loaded into the timer, and the prescaler value:

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 47
PIC18F452 Architecture

Timer 0:
• 16-bit Mode: Here, two timer registers named TMR0L and TMR0 are used to store
the 16-bit timer value.
• The low byte TMR0L is directly loadable from the data bus.
• The high byte TMR0 can be loaded through a buffer called TMR0H.
• During a read of TMR0L, the high byte of the timer (TMR0) is also loaded into
TMR0H, and thus all 16 bits of the timer value can be read.
• To read the 16-bit timer value, first we have to read TMR0L, and then read TMR0H
in a later instruction.
• Similarly, during a write to TMR0L, the high byte of the timer is also updated with
the contents of TMR0H, allowing all 16 bits to be written to the timer. Thus, to write
to the timer the program should first write the required high byte to TMR0H.
• When the low byte is written to TMR0L, then the value stored in TMR0H is
automatically transferred to TMR0, thus causing all 16 bits to be written to the
timer.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 48
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 49
PIC18F452 Architecture

Timer 1:
• The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter (two 8-bit registers; TMR1H and
TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• RESET from CCP module special event trigger
• Timer 1 is controlled by register T1CON

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 50
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 51
PIC18F452 Architecture

Timer 1:

●
Timer 1 can be operated as either a timer or a counter. When bit TMR1CS of register T1CON is low, clock
FOSC/4 is selected for the timer.
●
When TMR1CS is high, the module operates as a counter clocked from input T1OSI.
●
A crystal oscillator circuit, enabled from bit T1OSCEN of T1CON, is built between pins T1OSI and T1OSO
where a crystal up to 200KHz can be connected between these pins.
●
A prescaler is used in Timer 1 that can change the timing rate as a factor of 1, 2, 4, or 8.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 52
PIC18F452 Architecture

Timer 1:

●
Timer 1 can be configured so that read/write can be performed either in 16-bit mode or in two 8-bit
modes.
●
Bit RD16 of register T1CON controls the mode.
●
When RD16 is low, timer read and write operations are performed as two 8-bit operations.
●
When RD16 is high, the timer read and write operations are as in Timer 0 16-bit mode (i.e., a buffer is
used between the timer register and the data bus.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 53
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 54
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 55
PIC18F452 Architecture

Timer 2:
• Timer 2 is an 8-bit timer with the following features:
• 8-bit timer (TMR2)
• 8-bit period register (PR2)
• Programmable prescaler (1:1, 1:4, and 1:16)
• Programmable postscaler (1:1 upto 1:16)
• Interrupt when TM2 matches PR2
• Timer 2 is controlled from register T2CON

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 56
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 57
PIC18F452 Architecture

Timer 2:
• The TMR2 register is readable and writable, and is cleared on any device RESET.
• The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by
control bits T2CKPS1:T2CKPS0 (T2CON<1:0>).
• The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to
1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF,
(PIR1<1>)).
• The prescaler and postscaler counters are cleared when any of the following
occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or
Brown-out Reset)
• TMR2 is not cleared when T2CON is written.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 58
PIC18F452 Architecture

Timer 2:
• The Timer2 module has an 8-bit period register,
PR2.
• Timer2 increments from 00h until it matches
PR2 and then resets to 00h on the next
increment cycle.
• PR2 is a readable and writable register.
• The PR2 register is initialized to FFh upon RESET.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 59
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 60
PIC18F452 Architecture

Timer 3: Reading Assignment

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 61
PIC18F452 Architecture

Capture/Compare/PWM modules (CCP)

• The PIC18F452 microcontroller has two
capture/compare/PWM (CCP) modules, and they work
with Timers 1, 2, and 3 to provide capture, compare,
and pulse width modulation (PWM) operations.
• Each module has two 8-bit registers.
• Module 1 registers are CCPR1L and CCPR1H, and
module 2 registers are CCPR2L and CCPR2H.
• Module 1 is controlled by register CCP1CON, and
module 2 is controlled by CCP2CON.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 62
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 63
PIC18F452 Architecture

Capture Mode
• In Capture mode, CCPR1H:CCPR1L captures the 16-
bit value of the TMR1 or TMR3 registers when an
event occurs on pin RC2/CCP1.
• An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 64
PIC18F452 Architecture

Capture Mode
• The event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>).
• When a capture is made, the interrupt request flag
bit CCP1IF (PIR1<2>) is set; it must be cleared in
software.
• If another capture occurs before the value in register
CCPR1 is read, the old captured value is overwritten
by the new captured value.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 65
PIC18F452 Architecture

Capture Mode
• the RC2/CCP1 pin should be configured as an input by setting the
TRISC<2> bit.
• If the RC2/CCP1 is configured as an output, a write to the port can
cause a capture condition.
• The timers that are to be used with the capture feature (either
Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode.
• In Asynchronous Counter mode, the capture operation may not
work.
• The timer to be used with each CCP module is selected in the
T3CON register.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 66
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 67
PIC18F452 Architecture

Compare Mode
• In Compare mode, the 16-bit CCPR1 (CCPR2) register value is
constantly compared against either the TMR1 register pair value, or
the TMR3 register pair value.
• When a match occurs, the RC2/CCP1 (RC1/CCP2) pin is:
• driven High
• driven Low
• toggle output (High to Low or Low to High)
• remains unchanged
• The action on the pin is based on the value of control bits
CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the same time, interrupt flag
bit CCP1IF (CCP2IF) is set

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 68
PIC18F452 Architecture

Compare Mode
• Timer 1 or Timer 3 must be running in timer mode or in synchronized counter
mode, selected by register T3CON.
• When generate software interrupt is chosen, the CCP1 pin is not affected. Only
a CCP interrupt is generated (if enabled).
• an internal hardware trigger is generated, which may be used to initiate an
action.
• The special event trigger output of CCP1 resets the TMR1 register pair. This
allows the CCPR1 register to effectively be a 16-bit programmable period
register for Timer1.
• The special trigger output of CCPx resets either the TMR1 or TMR3 register
pair.
• Additionally, the CCP2 Special Event Trigger will start an A/D conversion if the
A/D module is enabled.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 69
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 70
PIC18F452 Architecture

PWM Module
• The pulse width modulation (PWM) mode produces a
PWM output at 10-bit resolution.
• A PWM output is basically a square waveform with a
specified period and duty cycle.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 71
PIC18F452 Architecture

PWM Module
• The module is controlled by Timer 2. The PWM period is
given by:

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 72
PIC18F452 Architecture

PWM Module
• The resolution of the PWM duty cycle is 10 bits.
• The PWM duty cycle is selected by writing the eight most significant bits
into the CCPR1L register and the two least significant bits into bits 4 and 5
of CCP1CON register.
• The duty cycle (in seconds) is given by:

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 73
PIC18F452 Architecture

PWM Module
• The steps to configure the PWM are as follows:
• Specify the required period and duty cycle.
• Choose a value for the Timer 2 prescaler (TMR2PS).
• Calculate the value to be written into the PR2 register using.
• Calculate the value to be loaded into the CCPR1L and
CCP1CON registers.
• Clear bit 2 of TRISC to make CCP1 pin an output pin.
• Configure the CCP1 module for PWM operation using register
CCP1CON.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 74
PIC18F452 Architecture

PWM Module
• Example: PWM pulses must be generated
from pin CCP1 of a PIC18F452
microcontroller. The required pulse period is
44ms and the required duty cycle is 50%.
Assuming that the microcontroller operates
with a 4MHz crystal, calculate the values to
be loaded into the various registers.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 75
 PIC18F452 Architecture

PWM Module
• Solution: Assuming a timer prescaler factor of 4,

The required steps are summarized as follows:

• Load Timer 2 with prescaler of 4 (i.e., load
T2CON) with 00000101 (i.e., 05H).
• Load 0AH into PR2.
• Load 16H into CCPR1L.
• Load 0 into TRISC (make CCP1 pin
output).
• Load 0CH into CCP1CON

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 76
PIC18F452 Architecture

Analog-to-Digital Converter (A/D) Module

• The A/D converts an analog input voltage into a digital number so it
can be processed by a microcontroller or any other digital system.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 77
PIC18F452 Architecture

Analog-to-Digital Converter (A/D) Module

• An A/D converter usually has a single analog input
and a digital parallel output.
• The conversion process is as follows:
• Apply the processed signal to the A/D input
• Start the conversion
• Wait until conversion is complete
• Read the converted digital data

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 78
PIC18F452 Architecture

Analog-to-Digital Converter (A/D) Module

• Most members of the PIC18F family contain a 10-bit A/D
converter.
• If the chosen voltage reference is +5V, the voltage step value is:

• Therefore, for example, if the input voltage is 1.0V, the converter

will generate a digital output of 1.0/0.00489 = 205 decimal.
• Similarly, if the input voltage is 3.0V, the converter will generate
3.0/0.00489 = 613.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 79
PIC18F452 Architecture

Analog-to-Digital Converter (A/D) Module

• The A/D converter used by the PIC18F452 microcontroller has eight channels,
named AN0–AN7, which are shared by the PORTA and PORTE pins.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 80
PIC18F452 Architecture

Analog-to-Digital Converter (A/D) Module

• The A/D converter has four registers.
• Registers ADRESH and ADRESL store the higher and lower results of
the conversion respectively.
• Register ADCON0 controls the operation of the A/D module, such as
selecting the conversion clock together with register ADCON1,
selecting an input channel, starting a conversion, and powering up
and shutting down the A/D converter.
• Register ADCON1 is used for selecting the conversion format,
configuring the A/D channels for analog input, selecting the
reference voltage, and selecting the conversion clock together with
register ADCON0.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 81
PIC18F452 Architecture

Analog-
to-Digital
Converte
r (A/D)
Module

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 82
PIC18F452 Architecture

Analog-
to-Digital
Converte
r (A/D)
Module

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 83
PIC18F452 Architecture

Analog-to-Digital Converter (A/D) Module

• The steps in carrying out an A/D conversion are as follows:
• Use ADCON1 to configure required channels as analog and configure the reference
voltage.
• Set the TRISA or TRISE bits so the required channel is an input port.
• Use ADCON0 to select the required analog input channel.
• Use ADCON0 and ADCON1 to select the conversion clock.
• Use ADCON0 to turn on the A/D module.
• Configure the A/D interrupt (if desired).
• Set the GO/DONE bit to start conversion.
• Wait until the GO/DONE bit is cleared, or until a conversion complete interrupt is
generated.
• Read the converted data from ADRESH and ADRESL.
• Repeat these steps as required.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 84
PIC18F452 Architecture

Analog-to-Digital Converter (A/D) Module

• For correct A/D conversion, the A/D conversion clock must be selected
to ensure a minimum bit conversion time of 1.6ms.
• The following Table gives the recommended A/D clock sources for
various microcontroller operating frequencies.

For example, if the

microcontroller is operated
from a 10MHz clock, the
A/D clock source should be
FOSC/16 or higher (e.g.,
FOSC/32).

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 85
PIC18F452 Architecture

Analog-to-Digital Converter (A/D) Module

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 86
PIC18F452 Architecture

Interrupts Module
• The PIC18F452 devices have multiple interrupt
sources (18) and an interrupt priority feature that
allows each interrupt source to be assigned a high
priority level or a low priority level.
• The high priority interrupt vector is at 000008h and
the low priority interrupt vector is at 000018h.
• High priority interrupt events will override any low
priority interrupts that may be in progress.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 87
PIC18F452 Architecture

Interrupts Module
• Interrupts can be useful in many applications such as:
• Time critical applications. For example, in an emergency such
as a power failure or fire in a plant the CPU may have to shut
down the system immediately in an orderly manner. In such
applications an external interrupt can force the CPU to stop
whatever it is doing and take immediate
• Performing routine tasks. A timer interrupt scheduled with
the required timing can divert the CPU from normal program
execution to accomplish the task at the precise time required
action.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 88
PIC18F452 Architecture

Interrupts Module
• Interrupts can be useful in many applications such as:
• Task switching in multi-tasking applications. In multi-tasking
applications, each task may have a finite time to execute its code.
Interrupt mechanisms can be used to stop a task should it
consume more than its allocated time.
• To service peripheral devices quickly. Some applications may need
to know when a task, such as an A/D conversion, is completed.
This can be accomplished by continuously checking the completion
flag of the A/D converter. A more elegant solution would be to
enable the A/D completion interrupt so the CPU is forced to read
the converted data as soon as it becomes available.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 89
PIC18F452 Architecture

Interrupts Module
• There are ten registers which are used to control interrupt
operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 90
PIC18F452 Architecture

Interrupts Module
• Every interrupt source (except INT0) has three bits to
control its operation. These bits are:
• A flag bit to indicate whether an interrupt has occurred.
This bit has a name ending in . . .IF
• An interrupt enable bit to enable or disable the interrupt
source. This bit has the name ending in . . .IE
• A priority bit to select high or low priority. This bit has a
name ending in . . .IP

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 91
PIC18F452 Architecture

Interrupts Module
• RCON Register
• The top bit of the RCON register, called IPEN, is
used to enable the interrupt priority scheme.
• When IPEN=0, interrupt priority levels are disabled
and the microcontroller interrupt structure is
similar to that of the PIC16 series.
• When IPEN = 1, interrupt priority levels are
enabled.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 92
PIC18F452 Architecture

Figure: RCON register bits

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 93
PIC18F452 Architecture

Interrupts Module
• Enabling/Disabling Interrupts—No Priority Structure
• When the IPEN bit is cleared, the priority feature is
disabled.
• All interrupts branch to address 00008H of the program
memory.
• In this mode, bit PEIE of register INTCON enables/disables
all peripheral interrupt sources.
• Similarly, bit GIE of INTCON enables/disables all interrupt
sources.
Hawassa University, Institute of Technology School of Electrical and
Computer Engineering 06/30/2021 94
PIC18F452 Architecture

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 95
PIC18F452 Architecture

Interrupts Module
• For an interrupt to be accepted by the CPU the following conditions must
be satisfied:
• The interrupt enable bit of the interrupt source must be enabled. For
example, if the interrupt source is external interrupt pin INT0, then bit
INT0IE of register INTCON must be set to 1.
• The interrupt flag of the interrupt source must be cleared. For example, if
the interrupt source is external interrupt pin INT0, then bit INT0IF of
register INTCON must be cleared to 0.
• The peripheral interrupt enable/disable bit PEIE of INTCON must be set to
1 if the interrupt source is a peripheral.
• The global interrupt enable/disable bit GIE of INTCON must be set to 1.

Hawassa University, Institute of Technology School of Electrical and

Computer Engineering 06/30/2021 96