Digital Design:

An Embedded Systems
Approach Using Verilog

Chapter 6
Implementation Fabrics
Verilog

Integrated Circuits
 Early digital circuits
 Relays, vacuum tubes, discrete transistors
 Integrated circuits (ICs, or “chips”)
 Manufacture of multiple transistors and
connections on surface of silicon wafer
 Invented in 1958: Jack Kilby at Texas
Instruments (TI)
 Rapid growth since then, and ongoing

04-06-2021 Mrs. Swetha B V DSDV(15/17EC663) 2

Verilog

IC Manufacture: Wafers
 Start with ingot of
pure silicon
 Saw into wafers &
polish
 Early wafers:
50mm
 Now 300mm

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 3

Verilog

IC manufacture: Processing
 Chemical processing steps based on
photolithography
 Ion implantation
 Etching a deposited film
 SiO2, polysilicon, metal
resist
mask
film
wafer
(a)
(b)

(c) (d) (e)

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 4
Verilog

IC Manufacture: Test & Packaging

 Defects cause some ICs to fail
 Test to identify which ICs don’t work
 Discard them when wafer is broken into
chips
 Their cost is amortized over working chips
 Yield depends (in part) on IC area
 Constrain area to reduce final IC cost
 Working chips are packaged and tested
further

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 5

Verilog

Exponential Trends
 Circuit size and complexity depends on
minimum feature size
 Which depends on manufacturing process
 Mask resolution, wavelength of light
 Process nodes (ITRS Roadmap)
 350nm (1995), 250nm (1998),
180nm (2000), 130nm (2002),
90nm (2004), 65nm (2007), 45nm (2010),
32nm (2013), 22nm (2016), 16nm (2019)
 Smaller feature size  denser, faster

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 6

Verilog

SSI and MSI

 In 1964, TI introduced 5400/7400 family
of TTL ICs
 Other manufacturers followed, making
7400 family a de facto standard
 Small-scale integrated (SSI)
 7400: 4 × NAND gate 7427: 4 × NOR gate
 7474: 2 × D flip-flop …
 Medium-scale integrated (MSI)
 7490: 4-bit counter 7494: 4-bit shift reg
 …
04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 7
Verilog

Other Logic Families

 Variations on electrical characteristics
 74L… : low power
 74S… : Schottky diodes  fast switching
 74LS… : compromise between speed and
power
 74ALS… : advances low-power Schottky
 74F… : fast
 CMOS families
 4000 family: very low power, 3–15V
 74HC…, 74AHC… : TTL compatible
04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 8
Verilog

Large Scale Integration

 1970s: LSI (thousands of transistors)
 Small microprocessors became feasible
 Custom LSI chips for high-volume
applications
 SSI/MSI mainly used for glue logic
 Later additions to 74xx… families
oriented toward glue-logic and
interfacing
 E.g., multibit tristate drivers, registers
 Other functions supplanted by PLDs
04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 9
Verilog

MSI Example: Counter/Display

74LS390: dual decade counter
CP0 Q0
 CP1 Q1
Q2
MR Q3

74LS08 glue

CP0 Q0 CP0 Q0 CP0 Q0 CP0 Q0

CP1 Q1 CP1 Q1 CP1 Q1 CP1 Q1
Q2 Q2 Q2 Q2
MR Q3 MR Q3 MR Q3 MR Q3

A a

74LS47: 7-segment decoder

B b
 C c
D d
e
f
LT g
RBI RBO

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 10

Verilog

MSI Example: Counter/Display

+V

CP CP0 Q0 A a
CP1 Q1 B b
Q2 C c
MR Q3 D d
e
+V f
LT g
RBI RBO

+V

CP0 Q0 A a
CP1 Q1 B b
Q2 C c
MR Q3 D d
e
+V f
LT g
RBI RBO

+V

CP0 Q0 A a
CP1 Q1 B b
Q2 C c
MR Q3 D d
e
+V f
LT g
RBI RBO

+V

CP0 Q0 A a
CP1 Q1 B b
Q2 C c
MR MR Q3 D d
e
+V f
LT g
RBI RBO

Mrs. Swetha B V DSDV(15/17EC81) 11

Verilog

VLSI and ASICs

 1980s: Very Large Scale Integration
 Then ULSI, then what?
 VLSI now just means IC design
 Application-specific ICs (ASICs)
 Enabled by CAD tools, foundry services
 Often designed for a range of related
products in a market segment
 Application-specific standard products (ASSPs)
 E.g., cell phone ICs

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 12

Verilog

ASIC Economics
 ASIC has lower unit cost than an FPGA
 But more design/verification effort
 Higher non-recurring engineering (NRE) cost
 Amortized over production run
 ASICs make sense for high volumes
 Full custom
 Design each transistor and wire
 High NRE, but best performance & least area
 Standard cell
 Use basic components from a foundry’s library

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 13

Verilog

Programmable Logic Devices (PLDs)

 PLDs can be programmed after
manufacture to vary their function
 C.f. fixed-function SSI/MSI ICs and ASICs
 Higher unit cost than ASIC
 But lower NRE
 Ideal for low to medium product volumes

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 14

Verilog

Programmable Array Logic (PALs)

 Introduced by Monolithic Memories Inc
in 1970s
 First widely-used PLDs
 Programmed by blowing fusible links in the
circuit
 Use a special programming instrument
 PAL16L8
 16 inputs, 8 active-low outputs
 PAL16R8
 16 inputs, 8 registered outputs
04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 15
Verilog

PAL16L8
… I8 · I10

26
22
23
24
25
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
0
1

I1 · I2 + I3 · I10 2
3
4 O1
5
6
7

I2 I1
8
9
10
11
12 IO2
13
14
15
I3

…
…

48
49
50
51
52 IO7
53
54
55

I8
56
57
58
59
60 O8
61
62
63

I9 I1 0

Mrs. Swetha B V DSDV(15/17EC81) 16

Verilog

PAL16R8 Output Circuit

AND D Q

array clk Q

 Feedback path is useful for

implementing FSMs

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 17

Verilog

Designing with PALs

 Useful even for simple circuits
 Single package solution lowers cost
 Describe function using Boolean
equations
 In HDL, or simple language such as ABEL
 Synthesize to fuse map file used by
programming instrument
 If design doesn’t fit
 Partition into multiple PALs or use a more
complex PLD

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 18

Verilog

Generic Array Logic (GALs)

 Programmable Output
Logic Macrocells
(OLMCs)
Use EEPROM technology
8

OLMC

10
 E.g., GAL22V10
Programmable
AND array

OLMC
…

10
…

OLMC 0
1

…
D Q 2
SP 3
8
AR Q
clk
OLMC

0
1

Mrs. Swetha B V DSDV(15/17EC81) 19

Verilog

Complex PLDs (CPLDs)

 Cramming multiple PALs into an IC
 Programmable interconnection network
 Use flash RAM technology to store configuration

M/C

I/O block
M/C
AND M/C
Interconnection network

array

…
M/C

Embedded
PAL
…

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 20

Verilog

FPGAs
 Field Programmable Gate Arrays
 Smaller logic blocks, embedded SRAM
 Thousands or millions of equivalent gates
… …
IO IO IO IO … … IO IO

IO LB LB LB LB … … LB LB IO
RAM
IO LB LB LB LB … … LB LB IO
IO LB LB LB LB … … LB LB IO
RAM
IO LB LB LB LB … … LB LB IO
…
…

…
…
IO LB LB LB LB … … LB LB IO Programmable
RAM
IO LB LB LB LB … … LB LB IO interconnect
IO IO IO IO … … IO IO
… …

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 21

Verilog

Logic Block Example

 Xilinx FPGA Logic Blocks
 Lookup Tables (LUTs) plus flip-flops
 E.g., Spartan-II COUT
YB
Y
LUT Carry

Too complex to
an d S
G4 I4 O
 G3 I3
Co n tro l
Lo g ic
D
CE
Q YQ
G2 I2

program LBs
G1 I1 clk
R

manually
F5 IN
BY
SR
XB

Let synthesis tools

X
 LUT Carry
an d
F4 I4 O S

map HDL code to

Co n tro l D Q XQ
F3 I3
Lo g ic CE
F2 I2
F1 I1 clk

LBs and program

R

the interconnect BX
CIN
CE
CLK

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 22

Verilog

I/O Blocks

 Typically allow for 0

registered or D
CE
Q 1

+V

combinational
clk

input/output, plus
0

D Q 1

tristates
CE
clk

 Programmable logic
levels, slew rate, D
CE
Q

input threshold, … clk

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 23

Verilog

Platform FPGAs
 Include embedded cores for special
applications
 Processor cores
 Signal processing arithmetic cores
 Network interface cores
 Embedded software can run from SRAM
in the FPGA
 Single-chip solution, reduces cost
 Avoids high NRE of ASIC
04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 24
Verilog

Structured ASICs
 Array of very simple logic elements
 Not programmable, no programmable
interconnect
 Customized by designing top metal
interconnection layer(s)
 Lower NRE than full ASIC design
 Performance close to full ASIC
 May become popular for mid-volume
applications
04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 25
Verilog

IC Packages
 ICs are encapsulated in protective
packages
 External pins for connected to circuit board
 Bond-wires or flip-chip connections

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 26

Verilog

Printed Circuit Boards (PCBs)

 Layers of conducting wires (copper)
between insulating material (fiberglass)
 Manufactured using photolithography and
etching
 Wires interconnect ICs and other
components
 External connections to other system
components

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 27

Verilog

Through-Hole PCBs
 IC package pins pass through drilled
holes
 Soldered to PCB wires that join the hole

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 28

Verilog

Surface Mount PCB

 IC package pins soldered to wires on
PCB surface
 Packages and PCB features are generally
smaller than through-hole

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 29

Verilog

Multichip Modules (MCMs)

 Several ICs on a ceramic carrier
 Can also include thin-film passives and
discrete components
 External connections for PCB mounting

 Ideal for high-density

applications
 E.g., cell phones

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 30

Verilog

Signal Integrity
 Signals propagate over bond wires,
package pins, PCB traces
 Various effects cause distortion and noise
 Signal integrity: minimizing these effects
 Propagation delay in PCB trace
 ≈½c  ≈150mm/ns
 If two traces differ in length
 Skew at arrival point can be significant
 Careful PCB design needed

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 31

Verilog

Ground Bounce
 Transient current flows when an output
switches logic level
 Parasitic inductance causes
voltage shift on power supply
+V

Bond-wire, lead and

& ground signals PCB inductance
IC within package
 Spikes on other
drivers
 Threshold shift on
receivers
Bond-wire, lead and
PCB inductance

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 32

Verilog

Minimizing Bounce
 Bypass capacitors between ground and +V
 0.01µF – 0.1µF, close to package pins
 Separate PCB planes for ground and +V
 Limit output slew rate
 Trade off against
high slew-rate
propagation delay
slew rate limited

signal layer
power plane
signal layers Vth
ground plane
signal layer

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 33

Verilog

Transmission Line Effects

 Occur when rise time is comparable to path delay
 Reflections interfere with transitions, resulting in
under/overshoot and ringing
 Can cause false/multiple switching
 Use PCB layout
techniques to overshoot
minimize effects ringing

2.5V VOH
2.0V VIH
1.5V
1.0V ringing
VIL
0.5V VOL
0.0V
undershoot

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 34

Verilog

Electromagnetic Interference
 Transitions cause electromagnetic fields
 Energy radiated from PCB traces
 Induces noise in other systems
 Subject to regulation
 Crosstalk
 Radiation to other traces in the system
 Particularly adjacent parallel traces
 PCB layout and slew-rate limiting can
minimize both
04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 35
Verilog

Differential Signaling
 Reduces susceptibility to noise
 Transmit a signal (SP) and negation (SN)
 At receiver, sense difference between them
 SP – SN
 Noise induced on both SP and SN
 (SP + VNoise) – (SN + VNoise) = SP – SN
SP
S
SN

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 36

Verilog

Summary
 Exponential improvements in IC
manufacturing
 SSI and MSI TTL logic families
 ASICs: full-custom and standard cell
 PALs, CPLDs, FPGAs, platform FPGAs
 IC packages for PCB assembly
 Through-hole and surface mount
 Signal integrity

04-06-2021 Mrs. Swetha B V DSDV(15/17EC81) 37