1/Chapter4

© DHBK 2005

Course contents
1. Introduction to microprocessor systems
2. The Intel 8088/8086 microprocessors
3. Assembly programming for 8086
4. Memory and I/O Interfacing
5. Interrupt
6. Direct memory access (DMA)
7. Real life microprocessors
 2/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 3/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.1.1 8086 pins
4.1.2 Bus demultiplexing and buffering
4.1.3 8284 and 8288
4.1.4 Timing diagrams of read/write cycles
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 4/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.1.1 8086 pins
4.1.2 Bus demultiplexing and buffering
4.1.3 8284 and 8288
4.1.4 Timing diagrams of read/write cycles
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 5/Chapter4
© DHBK 2005

4.1.1 8086 pins

M/IO (S2) 16 address/data bits
DT/R(S1) AD0-AD15

RD A16/S3
System cotrol signals
WR (LOCK)
A17/S4
DEN (S0) 4 MSB address bits
A18/S5
SS0
A19/S6
READY
BHE/S7
NMI 8086
INTR
CPU control signals HOLD(RQ/GT0)
RESET
MN/MX HLDA(RQ/GT1) Bus control signals
INTA(QS1)
TEST
CLK ALE(QS0)
Clock and Power Vcc
sources
GND
GND
 6/Chapter4
© DHBK 2005

4.1.1 8086 pins

• AD0-AD15:
 ALE =1: 16 address bits
 ALE=0: 16 data bits
• A19/S6-A16/S3
 4 MS address bits S4 S3
 4 status btis: 0 0 ES
 S6 is always 1
0 1 SS
 S5: status of IF
 S4, S3: status of segment registers being accessed 1 0 CS or No

• INTR: interrupt request 1 1 DS

 IF=1 and INTR=1 => accepts interrupt
• TEST
 If TEST =0, CPU is in wait state and executs NOP instruction
 7/Chapter4
© DHBK 2005

4.1.1 8086 pins

• NMI (Non-maskable interrupt)
 NMI=1 => INT 2 is called
• RESET
 1: resets the system and executes instructions at the address FFFF0H
• MN/MX
 1: min mode
 0: max mode
• BHE/S7:
 0: Bus High Enable
• RD
 0: CPU reads data from memory or I/O devices
• Pins at min mode
 M/IO
 1: memory access
 0: I/O access
 WR
 0: writes data to memory or I/O devices
 8/Chapter4
© DHBK 2005

4.1.1 8086 pins

• Pins at min mode
 INTA: interrupt acknowledge
 0: when INTR=1 and IF=1
 ALE: address latch enable
 DT/R: data transmit/receive
 1: transmit data
 0: receive data
 DEN: Data enable
 0: enable the external data buffer
 HOLD
 1: CPU stops and gives control to DMA
 HLDA (Hold Acknowledge)
 When HOLD=1, HLDA=1
 9/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.1.1 8086 pins
4.1.2 Bus demultiplexing and buffering
4.1.3 8284 and 8288
4.1.4 Timing diagrams of read/write cycles
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 10/Chapter4
© DHBK 2005

4.1.2 Bus demultiplexing and buffering

• Why?
 Address pins and data pins are shared
 Increase the current which can be driven by bus
• Supporting ICs:
 74LS373: latch
 74LS245: 2 ways bus transceiver
 74LS244: 1 way data buffer
 11/Chapter4
© DHBK 2005

4.1.2 Bus demultiplexing and buffering

M/IO M/IO
RD ‘244 RD
WR WR
BHE/S7 BH
A19/S6 74LS373 A19

A16/S3 G A16
A15

A8
A7
8086
A0

ALE G G
74LS373 74LS373

AD15 D15

‘245
AD8 G DIR D8
AD7 D7
‘245

AD0 G DIR D0
DEN
DT/R
 12/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.1.1 8086 pins
4.1.2 Bus demultiplexing and buffering
4.1.3 8284 and 8288
4.1.4 Timing diagrams of read/write cycles
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 13/Chapter4
© DHBK 2005
Clock generator 8284 and bus controller
8288
 14/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.1.1 8086 pins
4.1.2 Bus demultiplexing and buffering
4.1.3 8284 and 8288
4.1.4 Timing diagrams of read/write cycles
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 15/Chapter4
© DHBK 2005

4.1.4 Timing diagram

 16/Chapter4
© DHBK 2005

4.1.4 Timing diagram

• Symbols in timing diagrams:

Min max Units

CS 1 CS hold time 60 ns
1
2 CS to data valid 30 ns
Data
3 Data hold time 5 10 ns
2 3
 17/Chapter4
© DHBK 2005

4.1.4 Timing diagram

• One read/write cycle (bus cycle) of 8086 consists of 4
clock cycles T.
 5 MHz: 4*200 ns=800 ns
 T1:
 CPU sends out the address of memory or I/O devices, DT/R, M/IO, ALE
 T2:
 CPU sends the signals RD or WR, DEN and data on D0-D15 in case of
write cycle.
 CPU reads the READY signal at the end of T2
 T3:
 IF READY=0 => T3 becomes wait cycles Tw=n*T
 At the end of T3, CPU reads the data in case of read cycle.
 T4:
 Signals on buses are freed
 WR changes from 0 to 1 starting the memory write.
 18/Chapter4
© DHBK 2005

4.1.4 Timing diagram

 19/Chapter4
© DHBK 2005

4.1.4 Timing diagram

 20/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.2.1 Memory types
4.2.2 Address decoding
4.2.3 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 21/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.2.1 Memory types
4.2.2 Address decoding
4.2.3 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 22/Chapter4
© DHBK 2005

4.2.1 Memory types

• Non-volatile memory
 ROM (Read Only Memory)
 PROM (Programmable ROM)
 EPROM (Erasable programmable ROM)
 Flash
 EEPROM (Electrically Erasable Programmable ROM)
 FeRAM (Ferroelectric Random Access Memory)
 MRAM (Magnetoelectronic Random Access Memory)
• Volatile memory
 SRAM (Static RAM)
 SBSRAM (Synchronous Burst RAM)
 DRAM (Dynamic RAM)
 FPDRAM (Fast Page mode Dynamic RAM)
 EDO DRAM (Extended Data Out Dynamic RAM)
 SDRAM (Synchronous Dynamic RAM)
 DDR-SDRAM (Double Data Rate SDRAM)
 RDRAM (Rambus Dynamic RAM)
 23/Chapter4
© DHBK 2005

4.2.1 Memory types

A0 D0
Address A1 D1
Data
signal A2 D2

An-1 Dm-1

WR WE
CS OE

WR: write
WE: Write enable
Chip select RD OE: Output enable
CS: Chip Select
RD: read
 24/Chapter4
© DHBK 2005

EPROM

Isolator Floating gate

Gate
Source Cực cửa Drain
Cực nguồn Cực máng

n+ n+
p
 25/Chapter4
© DHBK 2005

EPROM

No free electrons at the floating gate

Many free
electrons
Vss
Vss Vss

Many free Many free

electrons electrons
n+ n+
p

D=Vss

G=Vss Few free electron,

No channel between Source
and Drain
S=Vss
 26/Chapter4
© DHBK 2005

EPROM

No free electrons at the floating gate

Vcc
Vss Vss

n+ n+
p

D=Vss

G=Vcc
A conducting channel
between Source and Drain

S=Vss
 27/Chapter4
© DHBK 2005

EPROM

Many elctrons being trapped in the floating gate

Vcc
Vss Vss

n+ n+
p

D=Vss

G=Vcc No channel between Source

and Drain

S=Vss
 28/Chapter4
© DHBK 2005

EPROM: Read
Vcc Vcc Vcc Vcc

Address

2-to-4 Decoder

2
MSB

2
LSB
4 to 1 Mux

Data
 29/Chapter4
© DHBK 2005
Read(0x6)
EPROM: Read
Vcc Vcc Vcc Vcc

0110

2-to-4 Decoder

01

10

2-to-4 Mux

0
 30/Chapter4
© DHBK 2005
Read(0x8)
EPROM: Read
Vcc Vcc Vcc Vcc

1000

2-to-4 Decoder

10

00

2-to-4 Mux

1
 31/Chapter4
© DHBK 2005

EPROM: Erase UV
Vcc Vcc Vcc Vcc light

Address

2-to-4 Decoder

2
MSB

2
LSB
2-to-4 Mux

Data
 32/Chapter4
© DHBK 2005
Write 1 at 0x2
12V
EPROM: Write
Vcc Vcc Vcc Vcc

Address
0010

2-to-4 Decoder

2
00
MSB

2
10
LSB
2-to-4 Mux
4-to-1

Data
 33/Chapter4
© DHBK 2005

EPROM
• Writing EPROM
 Using programmer at 12 V
 1 ms per bit
• Erase EPROM
 20 minutes under ultra-violate source
 Number of erase: 3 times
• Read EPROM
 100 ns
• EPROM 27xxx
 2708 (1K*8), 2716 (2K*8), 2732 (4K*8), 2764 (8K*8) 27128 (16K*8), 27256
(32K*8), 27512 (64K*8)
 34/Chapter4
© DHBK 2005

EPROM
• Example: 2716 EPROM

U2

8
A0 O0
9 Address
7 10
6 A1 O1 11
5 A2 O2 13
4 A3 O3 14
3 A4 O4 15 CE
2 A5 O5 16
1 A6 O6 17
23 A7 O7
22 A8
A9
19
A10 Output
20
18 OE
120 100
CE
21
VPP
450

2716
 35/Chapter4
© DHBK 2005

Comparison of ROM

ROM type Writing time Reading time Number of Size

writes

ROM NA 35 ns 0 Mbits

PROM 1s/bit 35 ns 1 128 Kbits

EPROM 1ms/bit 45 ns 3 16 Mbits
Flash 1s/2 KB 35 ns 1 million GBits
EEPROM 10 ms/page 200 ns 10000 Mbit
FeRAM 60 ns 50 ns 1000 billion 32 Mbits
MRAM 5ns 5ns 1015 4 Mbits
 36/Chapter4
© DHBK 2005

SRAM
Decoder selects one row

Mux selects one column

0110

1bit 1bit 1bit 1bit

2-to-4 Decoder cell cell cell cell

01
1bit 1bit 1bit 1bit
cell cell cell cell

1bit 1bit 1bit 1bit

4 cell cell cell cell

1bit 1bit 1bit 1bit

cell cell cell cell
10

2-to-4 Mux
4-to-1
 37/Chapter4
© DHBK 2005

SRAM bit cell

Bit line Bit line inverse

Word
Vcc

acts as
resistor
 38/Chapter4
© DHBK 2005

Storing SRAM bit cell

Bit line Bit line inverse

Word
Vcc

5V 0V

Current

assumption Stable state; storing bit ‘1’

Continuous power dissipation

 39/Chapter4
© DHBK 2005

Storing SRAM bit cell

Bit line Bit line inverse

Word
Vcc

0V 5V

Current

Assumption
Stable state; storing bit ‘0’

Continuous power dissipation

 40/Chapter4
© DHBK 2005

Read bit ‘1’ SRAM bit cell

Bit line Bit line inverse

Word
Vcc

5V 0V

Current

1 0
 41/Chapter4
© DHBK 2005

Read bit ‘0’ SRAM bit cell

Bit line Bit line inverse

Word
Vcc

0V 5V

Current

0 1
 42/Chapter4
© DHBK 2005

Write ‘1’ SRAM bit cell

Vcc Vcc

Word
Word
Vcc

Bit line
Bit R
Bit line
line inverse
0V
5V 5V
0V

Current

Current
Current
W.D’ W.D
 43/Chapter4
© DHBK 2005

SRAM
• Characteristics:
 6 transistors per bit: expensive!
 Volatile
 Fast: access time 5 ns
 Continuous power dissipation
 Size: 16 Mbit
• Application:
 Small and fast memory (cache)
 Not used for battery operated devices
• Example: 4016 (2K*8), 250 ns, 6264(8Kx8), 62128(16Kx8)
A0-A10
D0-D7
OE
WE
CS
 44/Chapter4
© DHBK 2005

Bit DRAM Word

line line

Address

1bit 1bit 1bit 1bit

2-to-4 Decoder cell cell cell cell
2
MSB
1bit 1bit 1bit 1bit
cell cell cell cell

1bit 1bit 1bit 1bit

4 cell cell cell cell

1bit 1bit 1bit 1bit

cell cell cell cell
2
LSB
2-to-4 Mux

Data
 45/Chapter4
© DHBK 2005
DRAM
Decoder selects one row

Mux selects on column

0110

1bit 1bit 1bit 1bit

2-to-4 Decoder cell cell cell cell

01
1bit 1bit 1bit 1bit
cell cell cell cell

1bit 1bit 1bit 1bit

4 cell cell cell cell

1bit 1bit 1bit 1bit

cell cell cell cell
10

2-to-4 Mux

Data
 46/Chapter4
© DHBK 2005
DRAM bit cell
Vcc/2
1 bit
Pre-
cell
charge
Word
line

Vcc/2 Vcc/2 Vcc/2 Bit line

Refresh

Sense
amplifier

MUX
 47/Chapter4
© DHBK 2005
Storing
DRAM bit cell
Vcc/2

Pre-
charge
Word
line
5V 0V 5V

0V 5V 5V

Vcc/2 Vcc/2 Vcc/2

30 fF in
Refresh

.2 m
Stores
.5 M e-

MUX
 48/Chapter4
© DHBK 2005

Reading DRAM bit cell

Vcc/2

Pre-
charge
Word
line
2.55V
5V 2.45V
0V 2.55V
5V
2.55V
2.5V
5V

0V 5V 5V

Vcc/2 Vcc/2 Vcc/2

Refresh

MUX
 49/Chapter4
© DHBK 2005

DRAM bit cell

• Read cycle
 1. Precharge
 2. RAS (Row Address Select): read all bits in the row being
selected. This reading changes the capacitor voltage
 3. Sense amplifying of corresponding columns
 4.a CAS (Column Address Select): Selects one column and outputs
the data
 4.b Refresh: restore the data from the row selected in step 2
 50/Chapter4
© DHBK 2005
Writing
DRAM bit cell
Vcc/2

Pre-
charge
Word
line
2.55V
5V 2.45V
0V
5V 2.55V
5V

0V 5V 5V

Vcc/2 Vcc/2 Vcc/2

Refresh

MUX
 51/Chapter4
© DHBK 2005

DRAM bit cell

• Write cycle
 1. Precharge
 2. RAS (Row Address Select): read all bits in the row being
selected. This reading changes the capacitor voltage
 3. Sense amplifying of corresponding columns
 4.a CAS (Column Address Select): select on column and load the
value that needs to be written to that column
 4.b Refresh: restore the original values of the row which was
selected in step 2 except for the bit which has just been written to.
© DHBK 2005 Refresh 52/Chapter4

Làm tươi DRAM bit cell

Vcc/2

Pre-
charge
Word
line
2.51V
5V
3V 2.49V
0V
2V 2.51V
5V
3V

2V
2.49V
0V 2.51V
3V
5V 2.51V
3V
5V

Vcc/2 Vcc/2 Vcc/2

Refresh

MUX
 53/Chapter4
© DHBK 2005

DRAM bit cell

• Refresh cycle
 1. Precharge
 2. RAS (Row Address Select): read all bits in the row being
selected. This reading changes the capacitor voltage.
 3. Sense amplifying of corresponding columns
 4. Refresh: restore the original values of the row which was
selected in step 2.
 54/Chapter4
© DHBK 2005

DRAM
• Characteristics:
 1 transistor per bit: cheap, however need DRAM controller
 Only consume power during access or refresh.
 Quite fast: access time 50 ns
 Each row needs to be refeshed every 4 ms
 Size: 4 Gbits
• Used in main memory for microprocessor systems
• Example: TMS 4464 (64K*4)

A0-A7
D0-D3 CAS: Column address select
OE WE
RAS: Row address select

CAS RAS
 55/Chapter4
© DHBK 2005

SRAM vs DRAM

Cost
SRAM

DRAM

Refresh
controller
Size
 56/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.2.1 Memory types
4.2.2 Address decoding
 Using NAND gates
 Using decoders 74LS138, 74LS139
 Using PROM
 Using PAL (Programmable Array Logic)
4.2.3 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 57/Chapter4
© DHBK 2005
4.2.2 Address decoding
Using NAND gates
• Example: Connect EPROM 2716 (2K * 8) with 8088
• Analysis:
 2716 2K*8 = 211*8 => memory chip has 11 address lines A10-A0
which will be connected to A10-A0 of 8088
 8088: 20 address signals A19-A0
 We have to select 2K memory segemt in 1M space
 EPROM: 00000H-003FFH: forbidden
 We can select: FF800H-FFFFFH which contains the starting up address
FFFF0H-FFFFFH
A19A18A17A16 A15A14A13A12 A11A10A9A8 A7 A6 A5 A4 A3 A2 A1 A0

• FF800: 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
1111 1111 1xxx xxxx xxxx
• FFFFF: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
 58/Chapter4
© DHBK 2005
4.2.2 Address decoding
Using NAND gates
A19A18A17A16 A15A14A13A12 A11A10A9A8 A7 A6 A5 A4 A3 A2 A1 A0
• FF800: 1111 1111 1000 0000 0000
1111 1111 1xxx xxxx xxxx
• FFFFF: 1111 1111 1111 1111 1111

A19
A18 8088 A
A17 A0-A10 8088 D
Bus
A16 D0-D7 Bus
A15
A14
CS OE
A13
A12
A11
RD
IO/M
 59/Chapter4
© DHBK 2005
4.2.2 Address decoding
Using decoders
• Example: Connect EPROM 2764 (8K*8) with 8088 to get 64KB EPROM starting
from address F0000H
• Analysis:
 EPROM 8K*8 = 213*8 => memory chip has 13 address lines A12-A0 which will be
connected to A12-A0 of 8088
 Need 8 EPROM 2764 because 64=8*8K

A19A18A17A16 A15A14A13A12 A11A10A9A8 A7 A6 A5 A4 A3 A2 A1 A0

IC 1
• F0000: 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
• F1FFF: 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
IC 2
• F2000: 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
• F3FFF: 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IC 3
• F4000: 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
• ...
F5FFF: 1111 0101 1111 1111 1111

...

IC 8
• FE000: 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
• FFFFF: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
 60/Chapter4
© DHBK 2005
4.2.2 Address decoding
Using decoders
• Using
U1 3-8 decoder 74LS138
1 15 C B A G2B G2A G1 y0 y1 y2 y3 y4 y5 y6 y7
2 A Y0 14
B Y1 x x x 1 x x 1 1 1 1 1 1 1 1
3 13
C Y2 12 x x x x 1 x 1 1 1 1 1 1 1 1
6 Y3 11 x x x x x 0 1 1 1 1 1 1 1 1
4 G1 Y4 10
G2A Y5 0 0 0 0 0 1 0 1 1 1 1 1 1 1
5 9
G2B Y6 7 0 0 1 0 0 1 1 0 1 1 1 1 1 1
Y7 0 1 0 0 0 1 1 1 0 1 1 1 1 1
0 1 1 0 0 1 1 1 1 0 1 1 1 1
74LS138
1 0 0 0 0 1 1 1 1 1 0 1 1 1
1 0 1 0 0 1 1 1 1 1 1 0 1 1
1 1 0 0 0 1 1 1 1 1 1 1 0 1
1 1 1 0 0 1 1 1 1 1 1 1 1 0
 61/Chapter4
© DHBK 2005
4.2.2 Address decoding
Using decoders
• Using 3-8 decoder 74LS138

A0-A12 A0-A12
A0-A10
D0-D7 D0-D7
A0-A10
2764
D0-D7
A0-A10
U1 RD 2764
OE D0-D7
2764
A0-A10
OE D0-D7
A13 1 15 2764
A0-A10
CS OE D0-D7
2 A Y0 14 A0-A10
A14 B Y1 2764
CS OE D0-D7
A0-A10
3 13 2764
CS OE D0-D7
A15 C Y2 12 2764
CS OE D0-D7
Y3
A16
6
G1 Y4
11 CS OE 2764
4 10 CS OE
IO/M 5 G2A Y5 9 CS
G2B Y6 7
A17 CS
Y7
A18
A19 74LS138
 62/Chapter4
© DHBK 2005
4.2.2 Address decoding
Using decoders
• Using dual 2-4 decoder 74LS139

1A 1Y0
1B 1Y1
1Y2
1G 1Y3

2A 2Y0
2B 2Y1
2Y2
2G 2Y3

• Example: Connect EPROM 27128 (16K*8) to 8088 to get 64

KB EPROM starting at address F0000H
 63/Chapter4
© DHBK 2005
4.2.2 Address decoding
Using decoders
• Using PROM TPB28L42 (512*8)

A0-A12 A0-A12
A0-A10
D0-D7 D0-D7
A0-A10
2764
D0-D7
A0-A10
RD 2764
OE D0-D7
2764
A0-A10
OE D0-D7
A13 A0 O0 2764
A0-A10
CS OE D0-D7
A14 A1 O1 A0-A10
2764
CS OE D0-D7
A15 A2 O2 A0-A10
2764
CS OE D0-D7
A16 A3 O3 2764
CS OE D0-D7
A17 A4 TPB28L42
O4 CS OE 2764
A18 A5
O5 CS OE
A19 A6
O6 CS
A7
CS
A8 O7
G

IO/M
 64/Chapter4
© DHBK 2005
4.2.2 Address decoding
Using PAL
 65/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.2.1 Memory types
4.2.2 Address decoding
4.2.3 Interfacing 8088 with memory
 Interfacing 8088 with ROM
 Interfacing 8088 with SRAM
 Interfacing 8088 with DRAM
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 66/Chapter4
© DHBK 2005

4.2.3 Interfacing 8088 with memory

• Principle:
 Direct interfacing:
 Access time permitted by CPU > memory access time + address
decoding time
 Interfacing with wait state insertion
 Access time permitted by CPU < memory access time + address
decoding time

8088 working at 5 MHz permits a memory access time less

than 420 ns
 67/Chapter4
© DHBK 2005

4.2.3 Interfacing 8088 with ROM

• Example: Connect 8088 with EPROM 2732-450 ns

A0-A11 A0-A11
A0-A10
D0-D7 D0-D7
A0-A10
2732
D0-D7
A0-A10
U1 RD 2764
OE D0-D7
2764
A0-A10
OE D0-D7
A12 1 15 F8000-F8FFF 2764
A0-A10
CS OE D0-D7
2 A Y0 14 F9000- A0-A10
A13 B Y1 F9FFF 2764
CS OE D0-D7
A0-A10
3 13 2764
CS OE D0-D7
A14 C Y2 12 2764
CS OE D0-D7
6 Y3 11
A15 G1 Y4 CS OE 2764
4 10 CS OE
IO/M 5 G2A Y5 9
G2B Y6 CS
A16 7 FF000-FFFFF
Y7 CS
A17
A18 Tw generator
74LS138
A19
To RDY1 of 8284
 68/Chapter4
© DHBK 2005
4.2.3 Interfacing 8088 with
SRAM
• Example: connect 8088 with SRAM 62256 (32K*8) to get
256 KB SRAM memory starting at address 00000H

A0-A14 A0-A14
A0-A10
D0-D7 D0-D7
A0-A10
62256
D0-D7
A0-A10
U1 RD 2764
OE D0-D7
WR WE 2764
A0-A10
OE D0-D7
A15 1 15 00000-07FFF 2764
A0-A10
CS OE D0-D7
2 A Y0 14 A0-A10
A16 B Y1
08000-0FFFF 2764
CS OE D0-D7
A0-A10
3 13 10000-17FFF 2764
CS OE D0-D7
A17 C Y2 12 2764
CS OE D0-D7
Y3
A18 6
G1 Y4
11 CS OE 2764
4 10 CS OE
IO/M 5 G2A Y5 9
G2B Y6 CS
7 38000-3FFFF CS
Y7
A19
74LS138
 69/Chapter4
© DHBK 2005
4.2.3 Interfacing 8088 with
DRAM
• Example: Connect 8088 with TMS 4464 (64K*4) DRAM to
get 128 KB DRAM starting at address 00000H

A0-A7
RA0-RA7
MA0-MA7 A0-A7

A8-A15 CA0-CA7 2x4464

RAS0 RAS
ALE ALE
CAS CAS
A16 REN1
RD ACR TMS 4500A
WR ACW
A0-A7
RDY RDY
RAS1
2x4464
CLK CLK RAS
A17
A18 CAS
A19 CS
IO/M
 70/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
 71/Chapter4
© DHBK 2005

4.3 Interfacing 8086 with memory

FFFFF FFFFE
FFFFD 8088 8086
FFFFC
FFFFB FFFFA
8 bit 16 bit
IO/M M/IO
BHE

00005 00004
00003 00002
BHE A0 Function
00001 00000
High bank Low bank
(Odd bank) (Even Bank)
0 0 Select 2 bank

0 1 Select high bank

1 0 Select low bank

1 1 No bank is selected
 72/Chapter4
© DHBK 2005

4.3 Interfacing 8086 with memory

• Example: Connect EPROM 2716 (2K * 8) with 8086 to have
memory with address range FF000H-FFFFFH
 Need 2 IC because 4KB=2*2KB

A19A18A17A16 A15A14A13A12 A11A10A9A8 A7 A6 A5 A4 A3 A2 A1 A0

• FF000: 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Low bank
• FFFFE: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

• FF001: 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 High bank

• FFFFF: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
 73/Chapter4
© DHBK 2005

4.3 Interfacing 8086 with memory

A19
A18
A17 A1-A11 A0-A10
D0-D7 D0-D7
A16
A15 2716
A14
CS OE
A13
A12
M/IO RD
A0
A19
A18
A17 A1-A11 A0-A10
D0-D7 D8-D15
A16
A15 2716
A14
CS OE
A13
A12
M/IO RD
BHE
 74/Chapter4
© DHBK 2005

4.3 4.3 Interfacing 8086 with memory

BHE
HRD
RD A1-A11 A0-A10
D0-D7 D0-D7
A0 LRD 2716

CS OE

LRD
A19
A18
A17 A1-A11 A0-A10
D0-D7 D8-D15
A16
A15 2716
A14
CS OE
A13
A12
M/IO HRD
 75/Chapter4
© DHBK 2005

4.3 Interfacing 8086 with memory

• Example: connect 8086 with SRAM 62256 (32K*8) to get
256 KB SRAM starting at address 00000H

BHE
HWR
WR

A0 LWR
 76/Chapter4
© DHBK 2005

4.3 Interfacing 8086 with memory

• Example: Design a memory system for 8086 with 64 KB
EPROM and 128 KB SRAM using SRAM 62256 (32K*8) and
EPROM 27128 (16K*8)
 77/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
4.4.1 Basic IO interfacing methods
4.4.2 IO device address decoding
4.4.3 Programmable Parallel Interface 8255A
4.4.4 Programmable keyboard/monitor controller 8279
4.4.5 Programmable timer 8254
4.4.6 Programmable serial interface 16550
4.4.7 DAC0830 and ADC0804
 78/Chapter4
© DHBK 2005

4.4.1 Basic IO interfacing methods

• IO interfacing with separate memory space:
FFFF Address: 0000H-FFFFH
M/IO=0
Vùng mở rộng

03FF Input/output data using IN, OUT

COM1
03F8
Điều khiển đĩa mềm Example:
03F0
CGA adapter IN AX, 00H
03D0
LPT1 IN AL, F0H
0378
Điều khiển ổ cứng IN AX, DX
0320
COM2
02F8
8255 OUT 00H, AX
0060
Định thời (8253)
OUT F0H, AL
0040 OUT DX, AX
Điều khiển ngắt
0020
0000 Điều khiển DMA
 79/Chapter4
© DHBK 2005

4.4.1 Basic IO interfacing methods

• IO interfacing with separate memory space:
 80/Chapter4
© DHBK 2005

4.4.1 Basic IO interfacing methods

• IO device and memory share the same memory space
FFFFF

M/IO=1

Input and output data using mov

instructions
I/O
Example:
MOV AX, [0FF3H]

00000

Memory + I/O
 81/Chapter4
© DHBK 2005

4.4.1 Basic IO interfacing methods

• Simple input device:
VCC

8
7
6
5
4
3
2
1
10K

11
10

12
13
14
15
16
9

U1

2 18
4 A1 Y1 16
6 A2 Y2 14
8 A3
A4
Y3
Y4
12 To CPU data bus
11 9
13 A5 Y5 7
15 A6 Y6 5
17 A7 Y7 3
A8 Y8
1
19 1OE
2OE

74ALS244
SEL

To address decoding circuit

 82/Chapter4
© DHBK 2005

4.4.1 Basic IO interfacing methods

• Example of simple output device:
VCC

330

U2

3 2
4 D0 Q0 5
7 D1 Q1 6
From CPU data 8 D2
D3
Q2
Q3
9
13 12
bus 14 D4 Q4 15
17 D5 Q5 16
18 D6 Q6 19
D7 Q7
11
CLK
1
OE

74ALS374
SEL
From address decoding circuit
 83/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
4.4.1 Basic IO interfacing methods
4.4.2 IO device address decoding
4.4.3 Programmable Parallel Interface 8255A
4.4.4 Programmable keyboard/monitor controller 8279
4.4.5 Programmable timer 8254
4.4.6 Programmable serial interface 16550
4.4.7 DAC0830 and ADC0804
 84/Chapter4
© DHBK 2005

4.4.2 IO device address decoding

• 8 bit or 16 bit address?
 Number of devices < 256: 8 bit A0-A7: 00H-FFH
 Number of devices >256: 16 bit A0-A15: 0000H-FFFFH
• 8 bit or 16 bit data?
 If device is 8 bit: select 1 address bank
 If device is 16 bit: select 2 banks

BHE A0
FFFF FFFE
FFFD FFFC
FFFB FFFA

D8-D15 D0-D7

0005 0004
0003 0002
0001 0000
High bank Low bank
(odd bank) (even Bank)
 85/Chapter4
© DHBK 2005

4.4.2 IO device address decoding

• Example: Decode address for 8 bit IO device at address
07H
 07H= 0000 0111

A0 A0
A1 D0-D7 D8-D15
A1
A2 D0-D7 A2 D0-D7
A3 A3
A4 A4
CS WE CS WE
A5 A5
A6 A6
A7 A7
WR WR
IO/M M/IO
BHE
8088 8086
 86/Chapter4
© DHBK 2005

4.4.2 IO device address decoding

• Example: Decode address for a 16 bit output device at
address 64H and 65H
 64H= 0110 0100
 65H= 0110 0101
D8-D15 D8-D15

CS WE
A1
A2
A3 WR
A4
A5
A6 D7-D0 D0-D7
A7
M/IO CS WE
 87/Chapter4
© DHBK 2005

4.4.2 IO device address decoding

• Example: Decode address for 8 bit IO devices at low bank
addresses 10H, 12H, 14H, 16H, 18H, 1AH, 1CH, 1EH
 10H=0001 0000
 12H=0001 0010
 ....
 1EH=0001 1110
U1

A1 1 15 10H
2 A Y0 14 12H
A2 3 B Y1 13 14H
A3 C Y2 12 16H
6 Y3 11 18H
A0 G1 Y4 1AH
4 10
M/IO 5 G2A Y5 9 1CH
A4 G2B Y6 7 1EH
A5 Y7
A6
A7 74LS138
 88/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
4.4.1 Basic IO interfacing methods
4.4.2 IO device address decoding
4.4.3 Programmable Parallel Interface 8255A
4.4.3.1 Structure of 8255A
4.4.3.2 Operating modes of 8255A
4.4.3.3 Programming 8255A
4.4.4 Programmable keyboard/monitor controller 8279
4.4.5 Programmable timer 8254
4.4.6 Programmable serial interface 16550
4.4.7 DAC0830 and ADC0804
 89/Chapter4
© DHBK 2005

4.4.3.1 Structure of 8255A

• TTL compatible IO interface for microprocessors
• Normally used for keyboard and printer interface in IBM PC
(in the form of a block in chipset)
• 24 IO pins, 3 operating modes
• In IBM PC, 8255 is connected to address 60H-63H
 90/Chapter4
© DHBK 2005

4.4.3.1 Structure of 8255A

 91/Chapter4
© DHBK 2005

4.4.3.1 Structure of 8255A

 92/Chapter4
© DHBK 2005

4.4.3.1 Structure of 8255A

RD
WR
 93/Chapter4
© DHBK 2005

4.4.3.2 Operating modes of 8255A

 94/Chapter4
© DHBK 2005

4.4.3.2 Operating modes of 8255A

• Mode 0: simple IO interfacing mode. Ports can be used as
buffered input port or latch output port.
• Mode 1: Allows port A and port B to work as input/output
devices with handshaking signals provided by
corresonding bits of Port C
• Mode 2: Allow port A to work as 2 directional device with
handshaking signals provided by PCH. Port B can work in
either mode 0 or mode 1.
 95/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 0

RD
WR
 96/Chapter4
© DHBK 2005 ; Lập trình cho 8255
MOV AL, 10000000B ; Port A, Port B mode 0, output
MOV
OUT
DX, 703H
DX, AL
Chế độ 0
; Thủ tục hiển thị LED từ dữ liệu chứa trong bộ nhớ
DISP PROC NEAR
Address PUSHF ; cất các thanh ghi vào ngăn xếp

of 8255 PUSH
PUSH
AX
BX
ports PUSH
PUSH
DX
SI
are ; Thiết lập các thanh ghi để hiển thị
MOV BX, 8 ;số LED
0700H- MOV AH, 7FH ;chọn LED đầu tiên 0111 1111
0703H MOV SI, OFFSET MEM-1 ; địa chỉ chứa dữ liệu
MOV DX,701H ; địa chỉ cổng B
;Hiển thị 8 số
DISP1: MOV AL, AH ;chọn 1 số
OUT DX, AL
DEC DX ; địa chỉ cổng A
MOV AL, [BX+SI] ; dữ liệu của 7 đoạn led
OUT DX, AL
CALL Delay ; trễ 1 ms
ROR AH, 1 ;số tiếp theo
INC DX ; địa chỉ cổng B
DEC BX ;giảm chỉ số
JNZ DISP1 ; lặp lại 8 lần
;khôi phục lại các thanh ghi
POP SI
POP DX
POP BX
POP AX
POPF
RET
DISP ENDP
 97/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 0
 98/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 0
 99/Chapter4
© DHBK 2005ROWS EQU 4 ; 4 hàng
COLS EQU 4 ; 4 cột
PORTA EQU 50H
PORTB EQU 51H
KEY PROC NEAR USES CX
CALL SCAN ;test all keys SCAN PROC NEAR USES BX
JNZ KEY ; if key closed MOV CL, ROWS ;form row mask
CALL DELAY ; đợi 10 ms MOV BH, OFFH
CALL SCAN SHL BH, CL
JNZ KEY MOV CX, COLS ;load column count
KEY1: MOV BL, OFEH ;get selection mode
CALL SCAN SCAN1:
JZ KEY1 ; if no key closed MOV AL, BL ;select column
CALL DELAY OUT PORTB, AL
CALL SCAN ROL BL, 1
JZ KEY1 IN AL, PORTA; read rows
PUSH AX ;cất mã hàng OR AL,BH
MOV AL, COLS ;cal starting row key CMP AL, 0FFH ;test for a key
SUB AL, CL JNZ SCAN2
MOV CH, ROWS LOOP SCAN1
MUL CH
MOV CL, AL SCAN2:
DEC CL RET
POP AX SCAN ENDP
KEY2:
ROR AL,1 ;find row position DELAY PROC NEAR USES CX
INC CL MOV CX, 5000 ;10ms (8MHZ)
JC KEY2 DELAY1:
MOV AL,CL ;move code to AL LOOP DELAY1
RET RET
KEY ENDP DELAY ENDP
 100/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 1
• Port A and port B work as input port with latch:
 Data is latched at port A, B until CPU is ready to read the data
 Port C provides handshaking signals.
 101/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 1
 102/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 1

PA0-PA7 ASCII D0-D7

STB
PC4 DAV

82C55 Keyboard
 103/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 1
• Bit5 EQU 20H
• PortC EQU 22H
• PortA EQU 20H

• Read PROC NEAR

• IN AL, PortC ; read PortC

• Test AL, Bit5 ; test IBF
• JZ READ ; if IBF=0
• IN AL, PortA ; read data
• RET
• Read Endp
 104/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 1
• Port A and port B work as output port with latch:
 Similar to mode 0
 Port C provides handshaking signals.

1
 105/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 1
 106/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 1

PB0-PB7 ASCII D0-D7

ACK
PC2 ACK

PC4 DS

82C55 Printer
 107/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 1
BIT1 EQU 2
PORTC EQU 62H
PORTB EQU 61H
CMD EQU 63H

PRINT PROC NEAR

;check printer ready
IN AL,PORTC ;get OBF
TEST AL, BIT1 ;test OBF
JZ PRINT ;if OBF=0

;send character to printer

MOV AL, AH ;get data
OUT PORTB, AL ;print data

RET
PRINT ENDP
 108/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 2
• Only available for port A
• Port A is 2 directional port
 109/Chapter4
© DHBK 2005
4.4.3.2 Operating modes of 8255A
Mode 2
 110/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
4.4.1 Basic IO interfacing methods
4.4.2 IO device address decoding
4.4.3 Programmable Parallel Interface 8255A
4.4.4 Programmable keyboard/monitor controller 8279
4.4.5 Programmable timer 8254
4.4.6 Programmable serial interface 16550
4.4.7 DAC0830 and ADC0804
 111/Chapter4
© DHBK 2005

4.4.4 8279
• Điều khiển bàn phím và màn hiển thị 8279:
 quét và mã hoá cho bàn phím tới 64 phím
 bộ đệm FIFO có thể chứa 8 ký tự
 Điều khiển màn hiển thị tới 16 số
 16*8 RAM để chứa thông tin về 16 số hiển thị
• Các tín hiệu chính:
 A0: chọn giữa chế độ dữ liệu hoặc điều khiển
 BD: xoá trắng màn hiển thị
 CLK: tín hiệu xung nhịp vào
 CN/ST (control/Strobe): cổng vào nối với
phím điều khiển của bàn phím
 CS : chip select
 DB7-DB0: bus dữ liệu 2 chiều
 IRQ: =1 khi có phím bấm
 OUTA3-OUTA0: dữ liệu tới màn hiển thị (bit cao)
 OUTB3-OUTB0: dữ liệu tới màn hiển thị (bit thấp)
 RD: cho phép đọc dữ liệu từ thanh ghi điều khiển hoặc trạng thái
 RL7-RL0: xác định phím được nhấn
 SHIFT: nối với phím shift của bàn phím
 SL3-SL0: tín hiệu quét màn hình và màn hiển thị
 WR: viết dữ liệu vào thanh ghi điều khiển hoặc thanh ghi dữ liệu
 112/Chapter4
© DHBK 2005
4.4.4 8279
Interfacing 8279 with 8088
 113/Chapter4
© DHBK 2005
4.4.4 8279
Interfacing 8279 with keyboard
 114/Chapter4
© DHBK 2005
4.4.4 8279
Interfacing 8279 with display
 115/Chapter4
© DHBK 2005
4.4.4 8279
Programming 8279
• Từ điều khiển: D7D6D5D4D3D2D1D0
 116/Chapter4
© DHBK 2005
4.4.4 8279
Programming 8279
 117/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
4.4.1 Basic IO interfacing methods
4.4.2 IO device address decoding
4.4.3 Programmable Parallel Interface 8255A
4.4.4 Programmable keyboard/monitor controller 8279
4.4.5 Programmable timer 8254
4.4.6 Programmable serial interface 16550
4.4.7 DAC0830 and ADC0804
 118/Chapter4
© DHBK 2005

4.4.5 Programmable timer 8254

 119/Chapter4
© DHBK 2005

4.4.5 Programmable timer 8254

 120/Chapter4
© DHBK 2005

4.4.5 Programmable timer 8254

 121/Chapter4
© DHBK 2005

4.4.5 Programmable timer 8254

 122/Chapter4
© DHBK 2005

4.4.5 Programmable timer 8254

 123/Chapter4
© DHBK 2005

4.4.5 Programmable timer 8254

 124/Chapter4
© DHBK 2005

4.4.5 Programmable timer 8254

 125/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
4.4.1 Basic IO interfacing methods
4.4.2 IO device address decoding
4.4.3 Programmable Parallel Interface 8255A
4.4.4 Programmable keyboard/monitor controller 8279
4.4.5 Programmable timer 8254
4.4.6 Programmable serial interface 16550
4.4.7 DAC0830 and ADC0804
 126/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 127/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 128/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 129/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 130/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 131/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 132/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 133/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 134/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 135/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 136/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 137/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 138/Chapter4
© DHBK 2005
4.4.6 Programmable serial interface 16550
 139/Chapter4
© DHBK 2005

Chapter 4: Memory and I/O Interfacing

4.1 8086 pins and supporting ICs 8284, 8288
4.2 Interfacing 8088 with memory
4.3 Interfacing 8086 with memory
4.4 I/O interfacing
4.4.1 Basic IO interfacing methods
4.4.2 IO device address decoding
4.4.3 Programmable Parallel Interface 8255A
4.4.4 Programmable keyboard/monitor controller 8279
4.4.5 Programmable timer 8254
4.4.6 Programmable serial interface 16550
4.4.7 DAC0830 and ADC0804
 140/Chapter4
© DHBK 2005

4.4.7.1 DAC
 141/Chapter4
© DHBK 2005

4.4.7.1 DAC
 142/Chapter4
© DHBK 2005

4.4.7.2 ADC
 143/Chapter4
© DHBK 2005

4.4.7.2 ADC
 144/Chapter4
© DHBK 2005

4.4.7.2 ADC