Unit -1

• Syllabus
• UNIT I
• Co- Design Issues: Co- Design Models,
Architectures, Languages, A Generic Co-design
Methodology.
• Co- Synthesis Algorithms: Hardware software
synthesis algorithms: hardware – software
partitioning distributed system co-synthesis.
 INTRODUCTION

• in traditional embedded system approach, the hardware and software

partitioning is done in early stage.

• the software group take care of the software architecture Development and
implementation.

• The hardware group are responsible for building the hardware required for the
product. classic design

• There are less interaction between both the groups.

• The development can be either serial or parallel.

hw sw
• Once the hardware and software are ready, the integration is
performed.

• The increasing competition in commercial market and the need for

Reduced ‘time –to-market’ the product call for a novel approach for
embedded system design in which the hardware and software are
co-developed instead of independently developing both.

• Digital systems designs consists of hardware components and

software programs that execute on the hardware platforms.
Defination of hardware and software co-design:

• Hardware/software co-design means meeting system-

level objectives by exploiting the synergism of hardware and
software through their concurrent design.

OR

• Hardware/Software co design is the design of cooperating

hardware components and software components in a single
design effort.
• Con current :
•
hardware and software developed at the same time on parallel
paths.

Integrated:

interaction between hardware and software developments to

produce designs that meet performance criteria and functional
specifications.
 Concurrent design
• Traditional design flow Concurrent (co design) flow
• start

start
hw sw
hw

Sw
y
Designed b
nt
independe
xperts Designed by Same group of
groups of e experts with cooperation
 Importance of co –design:

1. Improves Design quality, Design cycle time and cost

2. Reduces integration and test time.
3. supports Growing complexity of Embedded system
4. Takes advantage of advances in tools and
Technologies
a. Processor cores
b. High-level hardware synthesis capabilities
c. ASIC development.
 Why co design?
• Reduce time to market
• Achieve better design
• Explore alternative designs
• Good design can be found by balancing the HW/SW
• To meet strict design constraint
• power, size, timing, and performance trade-offs
• safety and reliability
• system on chip
 CO DESIGN FEATURES

• Enables Mutual influence of both HW AND

SW early in the design cycle.
• Enables evaluation of larger design space.
• Analyzing different HW AND SW partitions
• Enables fast verification.
• Faster exploration of the design space.
 CO DESIGN PROBLAM

• Specification of the system.

• Hardware and software partitioning
• Scheduling.
• Modeling the hardware and software system
during the Design process
 Motivations for co design
• Co design helps meet time-to-market because developed software can be
verified much earlier.

• co design improves overall system performance, Reliability, and cost effectiveness

because defects found in hardware can be corrected before tape-out.

• Co-design benefits the design of embedded systems and SOCS, which need hw/ sw
tailored for a particular application.

• faster integration: reduced design time and cost

• better integration: lower cost and better performance.
• Verified integration : lesser errors and re-spins
 Driving factors in hardware and software
co design
1. performance : The classic argument in favor of dedicated
hardware design has been increased Performance. more work
Done per clock cycle. increased performance is obtained by
reducing the flexibility of an application or by specializing the
architecture that the application is mapped onto.
2 Energy efficiency : Almost every electronic consumer product
today carries a battery( IPOD, PDA, mobile phone, blue tooth
device…etc). This makes these products energy-constrained. in
order to become sufficiently energy –efficient,
Consumer devices are implemented using a combination of
embedded software and dedicated hardware components.
Thus a well-known use of hardware-software co design is to trade
function specialization and energy –efficiency by moving the
flexible software of a design into fixed hardware.
• Power densities: power densities of modern high-end processors are
such that their performance can no longer be increased by making them
run faster. Instead ,there is a broad and fundamental shift toward parallel
computer architectures. However ,at this moment ,there is no dominent
parallel computer architecture that has a shown to cover all applications.
• Design complexity: Today, it is common to integrate multiple
microprocessors together with all related peripherals and hardware
components on a single chip(system-on-chip(soc)).modern soc are
extremely complex. The conception of such a component is impossible
without a detailed planning and design phase .extensive simulations are
required to test the design upfront ,before committing to a costly
implementation phase .since software bugs are easier to address than
hardware bugs, there is a tendency to increase the amount of software.
• Design cost: new chips are very expensive to
design as a result ,hardware designers make chips
programmable so that these chips can be reused
over multiple products or product generations. the
soc is a good example of this trend.
however, ‘programmability ‘can be found in many
different forms other than embedded processors:
reconfigurable systems are based on the same idea
of reuse-through –reprogramming.
Fundamental issues of hardware and software
co-design.
1.Selecting the model.
(specification)
2.Selecting the architecture.
(implementation)
3.Selecting the language.

4.Hardware and software partitioning.

 1.Selecting the model.

•Models are used for capturing and describing the system characteristics.

• A Model is a formal system consisting of objects and composition rules.

•It is hard to make a decision on which model should be followed in a particular

system design.

•Most often designers switch between a variety of models from the requirements
Specification to the implementation aspects of the system design.
 2.Selecting the architecture.

• A model only captures the system characteristics and does

not provide information on ‘ how the system can be
manufactured?’.

• the architecture specifies how a system is going to

implement in terms of the number and types of different
components and the interconnection among them.
 Different types of architecture

1. controller architecture.
2. data path architecture.
3. complex instruction set computing(CISC).
4. Reduced instruction set computing(RISC).
5.Very long instruction word computing(VLIW).
6. Single instruction multiple data(SIMD).
7. Multiple instruction multiple data(MIMD).
• The controller Architecture implements the finite state
machine model using a state register and two combinational
circuits.
• the state register holds the present state and the
combinational circuits implement the logic for next state and
output.

• The datapath Architecture is best suited for implementing

the data flow graph model where the output is generated as
a result of a set of predefined computations on the input data.
Finite state machine datapath Architecture
• The finite state machine datapath (FSMD) architecture
combines the controller architecture with datapath
architecture.
• It implement a controller with datapath.
• The controller generates the control input whereas the
datapath processes the data.
• The datapath contains two types of i/o ports, out of which
one act as the control port for receiving/sending the control
signal from /to the controller unit and the second i/o port
interfaces the datapath with external world for data input and
data output.
• Normally the datapath is implemented in a chip and the i/o
pins of the chip acts as the data input output ports for the
chip resident data path.
• A datapath represents a channel between the input
and output.
• The datapath may contain registers,counters,register
files, memories and ports along with high speed
arithmetic units.
• Ports connect the datapath to multiple buses.
• Most of the time the arithmetic are connected in
parallel with pipelining support for bringing high
performance.
 Complex instruction set computing(CISC)
Architecture
• The complex instruction set computing architecture
uses an instruction set representing complex
operations.
• It is possible for a cisc instruction set to perform a
large complex operation with a single instruction.
• E.g. reading a register value and comparing it with a
given value and then transfer the program execution
to a new address location is done using the CJNE
instruction for 8051 isa
• The use of a single complex instruction in place of
multiple simple instructions greatly reduces the
program memory access and program memory size
requirement.

• It requires additional silicon for implementing

microcode decoder for decoding the CISC instruction.

• The datapath for the CISC processor is complex.

 Reduced instruction set computing(RISC)
Architecture
• The reduced instruction set computing(RISC)
Architecture uses instruction set representing simple
operations.
• It requires the execution of multiple RISC instruction
to perform a complex operation.
• The datapath of RISC architecture contains a large
register file for storing the operands and output.
• RISC instruction set is designed to operate on
registers.
• RISC architecture supports extensive pipelining.
• The very long instruction word(VLIW) Architecture implements
multiple functional units (ALUs, multiplier, etc.) in the datapath.
• The VLIW instruction packages one standard instruction for
functional unit of the datapath.
• Parallel processing architecture implements multiple
concurrent processing Elements (PEs) and each processing
element may associate a datapath containing register and local
memory.
• Single instruction multiple data (SIMD)and multiple instruction
multiple data (MIMD) architecture are examples for parallel
processing architecture.
• In SIMD architecture a single instruction is executed in
parallel with the help of the processing Elements.
• the scheduling of the instruction execution and controlling
of each PE is performed through a single controller.
• The SIMD architecture forms the basis of re-configurable
processor.
• In MIMD architecture ,the processing Elements execute
different instructions at a given point of time.
• The MIMD architecture forms the basis of multiprocessor
systems.
• The PEs in a multiprocessor system communicates through
mechanisms like shared memory and message passing.
 Selecting the language

• A programming language captures a ‘computational model’ and maps it into

architecture.
• There is no hard and fast rule to specify this language should be used for
capturing this model.
• A model can be captured using multiple programming languages like c, c++,
c#, java etc. For software implementations and languages like
VHDL,SYSTEM C, VERILOG, etc. for hardware implementations.
• A single language can be used for capturing a variety of models.
• Certain languages are good in capturing certain computational model.
• for example ,c++ is a good candidate for capturing an object oriented model.
• The only pre-requisite in selecting a programming language for capturing a
model is that the language should capture the model easily.
 Partitioning system requirements into hardware and
software

• From an implementation perspective, It may be

possible to implement the system requirements in
either hardware or software(firmware).
• it is a tough decision making task to figure out which
one to opt.
• Various hardware software trade-offs are used for
making a decision on the hardware –software
partitioning.
 Computational models in embedded
design
• The commonly used computational models in embedded
system design are

1. FINITE STATE MACHINE

2. DATA FLOW GRAPH.
3. FINITE STATE MACHINE WITH DATAPATH.
4. HIERARCHICAL CONCURRENT FINITE STATE MACHINE.
5. PROGRAMMING LANGUAGE.
6. PROGRAM STATE MACHINE.
 FINITE STATE MACHINE
• This is the most popular model for describing control systems.
Here the temporal behavior of such system is most naturally
represented in the form of states, and transitions between
states.
• the FSM model consists of a set of states, a set of transitions
between states and a set of action associated with these
states or transitions.
• the finite state machine can be defined abstractly as the
quintuple
{S,I,O,F,H}
• <s, I ,o, f, h>
• S, I and o represent the a set of states, a set of
inputs and a set of output.
• F and h represent the next state and the output
functions.
• F assigns to every pair of state and input symbols,
another state symbols.
• The FSM model assumes that transitions from one
state to another occur only when input symbols
change.
• The next state function f defines what the state of
the FSM will be after the input symbol change.
• the output function h determines the output value
in the present state.
• there are 2 different types of finite state machine
which correspond to two different definitions of the
output function .
1. state based or moore type
2. input based or melay type
• 1.state based or moore type:
for which h is defined as a mapping s->o in other words ,an
output symbol is assigned to each state of the FSM and outputed
during the time the FSM is in that particular state.

• 2. input based or melay type:

FSM, for which h is defined as the mapping s* i->o
The output depends upon the present state value and present input.
 2. data flow graph
• It is the most popular model for describing computational
intensive systems. Because mathematical equations can be
naturally represented by a directed graph in which the nodes
represent operations or functions and the arcs represent the
order in which the nodes are executed.

• the data flow model of computation is based on two

principles.
1. asynchrony
2. functionality
 3.Finite state machine with datapath

• We must combine the features of the FSM and DFG

models. One solution is to divide time in to equal
time intervals, called states, and allocate one or more
status for each node in the DFG.
• because DFG computations are executed in a data
path. we call this modal a finite state machine with
datapath.
• FSM is a quintuple
<S, I, O, f, h>
• we define a variables set V which defines the state
of the datapath by defining the values of all variables
in each state.
• we can separate the set of FSMD inputs into a set
of FSM inputs Ic and a set of datapath inputs Id .
I=Ic*Id
Similarly the output set consists of FSM output Oc and
datapath output OD
O=Oc* OD
HIERARCHICAL CONCURRENT FINITE -STATE MACHINE.

• HIERAR CHICAL CONCURRENT FINITE -STATE MACHINE is

essentially an extension of the FSM model which adds support
for hierarchy and concurrency, thus eliminating the potential
for state and explosion that occurred when describing
hierarchical and concurrent systems with FSM models.
• Like the FSM , The HCFSM model consists of a set of states
and a set of transitions .
• unlike the FSM, however ,in the HCFSM each state can be
further decomposed in to a set of substates, thus modelling
hierarchy. Further more ,each state can also be decomposed
into concurrent substates, which execute in parallel and
communicate through global variables.
• The transitions in this model can be either
structured or unstructured , with structured
transitions allow only between two states on the
same level of hierarchy, while unstructured
transitions may occur between any two states
regardless of their hierarchical relationship.
 Programming language
• Programming language provide a heterogeneous
model that can support data, activity and control
modelling.

• There are two major types of programming

languages
• 1. imperative
2.declarative
• The IMPERATIVE class includes languages like C and
Pascal which use a control-driven model of
execution, in which statements are executed in the
order written in the program.
• Declarative languages such as LISP and PROLOG. they
model execution through demand-driven or pattern-
driven computation. The key difference here is that
declarative languages specify no explicit order of
execution. Because the sequence of execution is
based on a set of logic rules or functions.
• A programming language would model small activities
by means of statements,and large activities by means of
FUNCTIONS OR PROCEDURES. Which can also serve as a
mechanism for supporting hierarchy with in the system.

• these programming languages can also model control

flow , by using control constructs that specify the order
in which activities are to be performed.
 PROGRAM STATE MACHINE

• Program -state machines:

• this model basically consists of a hierarchy of program-states, in

which each program-state represents a distinct mode of computation. At any
given time, only subset of program-states will be active, i.e actively carrying
out their computations.

• within its hierarchy, the model would consist of both composite and leaf
program –states.

• a composite program-state is one that can be further decomposed into

either concurrent or sequential program –substates.
• A sequentially decomposed program-state will
contain a set of transition arcs, which represent the
sequencing between the program-substates.

• There are two types of transition arcs.

• 1. TRANSITION-ON-COMPLETION arc.
2. TRANSITION-IMMEDIATELY arc
 architectures

• we have demonstrated how a model is used to describe a

system’s functionality, data, control,and structure.

• An architecture is intended to supplement these descriptive

models by specifying how the system will actually be
implemented.

• The goal of an architecture design is to describe the number of

component , the type of each component, and the type of
each connection among these various components in a system.
1.Controller architecture
 2.Data path architecture

• Data path can be used for implementation of DFGs in

many applications where a fixed computation must
be performed repeatedly on different set of data , as
is the case in the digital signal processing
(DSP)systems used for digital filtering, image
processing, and multimedia.
• a datapath architecture often consists of high-
speed arithmetic units, connected in parallel and
heavily pipelined in order to achieve a high
throughput.
• A general- purpose datapath can compute DFGs in which each
node is scheduled in to one or more control steps or clock
cycles.

• A datapath may include counters , registers, register-files and

memories with a varied number of ports that are connected
with several buses.

• these same buses can be used to supply operands to

functional units as well as to supply results back to storage
units.
• It is also possible for the functional units to obtain operands from
several buses, through this would require the use of a selector in
front of each input.

• it is also possible for each unit to have input and output latches
which are used to temporarily store the input operands or results.

• such latching can significantly shorten the amount of time that

the buses will be used for operand and result transfer ,
And thus can increase the traffic over these buses.
FSMD ARCHITECTURE
CISC ARCHITECTURE
RISC ARCHITECTURE
VLIW ARCHITECTURE
Parallel Architecture
languages
 1.3.1 CONCURRENCY

• Concurrency can be classified in to two groups

1 . Data –driven or control driven

2. pipelined concurrency
1.3.2 State transitions
1.3.3 HIERARCHY