Analog Digital Electronics (ADE) - Sequential Circuits
Analog Digital Electronics (ADE) - Sequential Circuits
ADE-08
Basic building
blocks include:
◻Inp ◻Outpu
uts ◻Combinational ts
circuit
◻Memory
element
Types of sequential circuits
INPUTS
Q
Flip flops(conti…)
◻ As a FF has two stable states , it is called a Bistable
Multivibrator .
◻ As a FF stores one bit binary information ,it is called a
Binary or one-bit Memory.
◻ A flip flop can have one or more inputs and two outputs
namely Q and Q.
◻ When Q=1, FF is said to be in High state or 1state or
SET state.
◻ When Q=0, FF is said to be in Low state or 0 state or
RESET state or CLEAR state.
Creation of memory elements
◻ Any device or circuit that has 2 stable states is said to
be bistable . EX:-
� (1) A toggle switch(as shown in fig) has 2 stable
states(Either up or down,eiher on or off)-So the switch is
also said to have memory since it will remain as set until
some one changes its position.(physical example)
� (2)A flip flop (as shown in fig )has 2 stable states(either 0
or +5 Vdc,either logic 0 or logic 1)-So the FF is also has
memory since its output will remain as set until some
thing is done to change it .(logical example)
◻ NOTE:- Any bistable device can be used to store one
binary digit(bit)-logic 0 or logic 1
Creation of memory elements (conti..)
◻ Construction of FF’s:-
� We can create memory with the boolean gates.
� If you arrange the gates correctly, they will remember an
input value . This simple concept is the basis of RAM
(random access memory) in computers, and also makes it
possible to create a wide variety of other useful circuits .
� Memory relies on a concept called feedback. If you follow
the feedback path, you can see that if Q happens to be 1, it
will always be 1. If it happens to be 0, it will always be 0.
One of the easiest way to construct a FF is to connect 2
inverters in series with a feed back line (as shown in fig).
�
Creation of memory elements (conti..)
L
time
Level triggering
Flip flops contd…
◻ FLIP
FLIP FLOP FLOP◻ Q
◻
Q ENAB
LE
◻ Q
Q
◻
FLIP FLOP
Q
CLK/ENAB
LE
Q
FF with Clock signal
Positive Negative
Pulse Pulse
D SR
FF FF
FF
JK
T FF FF
S
1 Q
(set)
2 Q
’’
R
(reset
)
Points to remember about NOR and
NAND gates
◻ Nor gate:
� Any input is 1 output is 0 .
� Any input is 0 output is complement of other input.
◻ NAND gate:-
� Any input is 0 output is 1
� Any input is 1 output is complement of other input.
Truth table
S R Q(present Q(Next)
STATE
) or Qn or Qn+1 S R Qn+1 STA
TE
0 0 0 0 No change /Hold/Storage
state
0 0 1 1 No change/Hold/Storage 0 0 Qn HOL
state D
0 1 0 0 Reset
0 1 0 RES
0 1 1 0 Reset ET
1 0 0 1 Set
1 0 1 1 Set 1 0 1 SET
1 1 0 X Undefined/Invalid/in
determined/Restricted
combination 1 1 ? INV
1 1 1 X Undefined/Invalid/in ALI
determined/Restricted D
combination
R-S latch(using
NAND)
Symbols: Set Normal
S Q
FF
R Q
Reset Comple-
mentary
Truth Table:
Mode of Operation Inputs Outputs
S R Qn+1 Q’n+1
Prohibited 0 0 1 1
Set 0 1 1 0
Reset 1 0 0 1
Hold 1 1 Qn Q’n
L
? High
H
Mode of operation = ? Set
H
? High
H
Mode of operation = ? Hold
H
? Low
L
Mode of operation = ? Reset
TEST
R 1 0 Reset
Q
0 1 Set
1 1 Hold
◻ What does it do? 0 0 1/1
Q
S ’
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