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Ch.2 Performance Issues: Computer Organization and Architecture

This document discusses improvements in computer processor performance over time. It covers three main points: 1. Processor performance has increased through shrinking transistor sizes, larger and faster caches, and changes to processor organization and architecture like pipelining and parallelism. However, power dissipation and physical limits to shrinking components have diminished returns. 2. Modern processors use multiple cores on a chip to improve performance. This provides better performance than a single, more complex processor while using less power. 3. Processor instruction sets and architectures have evolved over time through additions to the x86 architecture to improve functionality while maintaining backwards compatibility. Embedded systems often use the ARM architecture with requirements like low power.

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Zhen Xiang
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157 views

Ch.2 Performance Issues: Computer Organization and Architecture

This document discusses improvements in computer processor performance over time. It covers three main points: 1. Processor performance has increased through shrinking transistor sizes, larger and faster caches, and changes to processor organization and architecture like pipelining and parallelism. However, power dissipation and physical limits to shrinking components have diminished returns. 2. Modern processors use multiple cores on a chip to improve performance. This provides better performance than a single, more complex processor while using less power. 3. Processor instruction sets and architectures have evolved over time through additions to the x86 architecture to improve functionality while maintaining backwards compatibility. Embedded systems often use the ARM architecture with requirements like low power.

Uploaded by

Zhen Xiang
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Ch.

2 Performance
Issues
Computer Organization and Architecture
Improvements in Chip Organization
and Architecture
 Increase hardware speed of processor
 Fundamentally due to shrinking logic gate size
 More gates, packed more tightly, increasing clock rate
 Propagation time for signals reduced

 Increase size and speed of caches


 Dedicating part of processor chip
 Cache access times drop significantly

 Change processor organization and architecture


 Increase effective speed of execution
 Parallelism
Problems with Clock Speed and
Login Density
 Power
 Power density increases with density of logic and clock speed
 Dissipating heat
 RC delay
 Speed at which electrons flow limited by resistance and capacitance of metal wires
connecting them
 Delay increases as RC product increases
 Wire interconnects thinner, increasing resistance
 Wires closer together, increasing capacitance
 Memory latency
 Memory speeds lag processor speeds
 Solution:
 More emphasis on organizational and architectural approaches
Intel Microprocessor Performance
Increased Cache Capacity

 Typically two or three levels of cache between processor and


main memory
 Chip density increased
 More cache memory on chip
 Faster cache access

 Pentium chip devoted about 10% of chip area to cache


 Pentium 4 devotes about 50%
More Complex Execution Logic

 Enable parallel execution of instructions


 Pipeline works like assembly line
 Different stages of execution of different instructions at same time
along pipeline
 Superscalar allows multiple pipelines within single processor
 Instructions that do not depend on one another can be executed in
parallel
Diminishing Returns

 Internal organization of processors complex


 Can get a great deal of parallelism
 Further significant increases likely to be relatively modest
 Benefits from cache are reaching limit
 Increasing clock rate runs into power dissipation problem
 Some fundamental physical limits are being reached
New Approach – Multiple Cores

 Multiple processors on single chip


 Large shared cache
 Within a processor, increase in performance proportional to
square root of increase in complexity
 If software can use multiple processors, doubling number of
processors almost doubles performance
 So, use two simpler processors on the chip rather than one
more complex processor
 With two processors, larger caches are justified
 Power consumption of memory logic less than processing logic
x86 Evolution (1)

 8080

 first general purpose microprocessor

 8 bit data path

 Used in first personal computer – Altair

 8086 – 5MHz – 29,000 transistors

 much more powerful

 16 bit

 instruction cache, prefetch few instructions

 8088 (8 bit external bus) used in first IBM PC

 80286

 16 Mbyte memory addressable

 up from 1Mb

 80386

 32 bit

 Support for multitasking

 80486

 sophisticated powerful cache and instruction pipelining

 built in maths co-processor


x86 Evolution (2)

 Pentium
 Superscalar
 Multiple instructions executed in parallel
 Pentium Pro
 Increased superscalar organization
 Aggressive register renaming
 branch prediction
 data flow analysis
 speculative execution
 Pentium II
 MMX technology
 graphics, video & audio processing
 Pentium III
 Additional floating point instructions for 3D graphics
x86 Evolution (3)

 Pentium 4
 Note Arabic rather than Roman numerals

 Further floating point and multimedia enhancements

 Core
 First x86 with dual core

 Core 2
 64 bit architecture

 Core 2 Quad – 3GHz – 820 million transistors


 Four processors on chip

 x86 architecture dominant outside embedded systems

 Organization and technology changed dramatically

 Instruction set architecture evolved with backwards compatibility

 ~1 instruction per month added

 500 instructions available

 See Intel web pages for detailed information on processors


Embedded Systems
ARM

 ARM evolved from RISC design


 Used mainly in embedded systems
 Used within product
 Not general purpose computer
 Dedicated function
 E.g. Anti-lock brakes in car
Embedded Systems Requirements

 Different sizes
 Different constraints, optimization, reuse
 Different requirements
 Safety, reliability, real-time, flexibility, legislation
 Lifespan
 Environmental conditions
 Static v dynamic loads
 Slow to fast speeds
 Computation v I/O intensive
 Descrete event v continuous dynamics
Possible Organization of an Embedded System
ARM Evolution

 Designed by ARM Inc., Cambridge, England


 Licensed to manufacturers
 High speed, small die, low power consumption
 PDAs, hand held games, phones
 E.g. iPod, iPhone
 Acorn produced ARM1 & ARM2 in 1985 and ARM3 in 1989
 Acorn, VLSI and Apple Computer founded ARM Ltd.
ARM Systems Categories

 Embedded real time


 Application platform
 Linux, Palm OS, Symbian OS, Windows mobile
 Secure applications
Performance Assessment
Clock Speed

 Key parameters
 Performance, cost, size, security, reliability, power consumption
 System clock speed
 In Hz or multiples of
 Clock rate, clock cycle, clock tick, cycle time
 Signals in CPU take time to settle down to 1 or 0
 Signals may change at different speeds
 Operations need to be synchronised
 Instruction execution in discrete steps
 Fetch, decode, load and store, arithmetic or logical
 Usually require multiple clock cycles per instruction
 Pipelining gives simultaneous execution of instructions
 So, clock speed is not the whole story
System Clock
Instruction Execution Rate

 Millions of instructions per second (MIPS)


 Millions of floating point instructions per second (MFLOPS)
 Heavily dependent on instruction set, compiler design, processor
implementation, cache & memory hierarchy
Benchmarks

 Programs designed to test performance


 Written in high level language
 Portable
 Represents style of task
 Systems, numerical, commercial
 Easily measured
 Widely distributed
 E.g. System Performance Evaluation Corporation (SPEC)
 CPU2006 for computation bound
 17 floating point programs in C, C++, Fortran
 12 integer programs in C, C++
 3 million lines of code
 Speed and rate metrics
 Single task and throughput
SPEC Speed Metric
 Single task
 Base runtime defined for each benchmark using reference
machine
 Results are reported as ratio of reference time to system run time
 Trefi execution time for benchmark i on reference machine
 Tsuti execution time of benchmark i on test system

• Overall performance calculated by averaging ratios


for all 12 integer benchmarks
— Use geometric mean
– Appropriate for normalized numbers such as ratios
SPEC Rate Metric
 Measures throughput or rate of a machine carrying out a number of tasks
 Multiple copies of benchmarks run simultaneously
 Typically, same as number of processors
 Ratio is calculated as follows:
 Trefi reference execution time for benchmark i
 N number of copies run simultaneously
 Tsuti elapsed time from start of execution of program on all N processors until
completion of all copies of program
 Again, a geometric mean is calculated
Amdahl’s Law

 Gene Amdahl [AMDA67]


 Potential speed up of program using multiple processors
 Concluded that:
 Code needs to be parallelizable
 Speed up is bound, giving diminishing returns for more processors
 Task dependent
 Servers gain by maintaining multiple connections on multiple
processors
 Databases can be split into parallel tasks
Amdahl’s Law Formula
• For program running on single processor
— Fraction f of code infinitely parallelizable with no scheduling overhead
— Fraction (1-f) of code inherently serial
— T is total execution time for program on single processor
— N is number of processors that fully exploit parralle portions of code

 Conclusions
 f small, parallel processors has little effect
 N ->∞, speedup bound by 1/(1 – f)
 Diminishing returns for using more processors
References

 https://angsila.cs.buu.ac.th/~krisana/886320/handout/02_Comput
er-Evolution.ppt

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