Introduction to State Machine

The state machine

Definition : A state machine is a system that can be used to
describe the system in terms of set of states that the system
goes through.
In this type of system, memory capability of system is a must.
Also, the state machine must have a set of inputs and outputs.
Clocked synchronous FSM
• Clocked:
all storage elements employ a clock input (i.e. all storage
elements are flip-flops)
• Synchronous:
all of the flip flops use the same clock signal
• FSM
state machine is simply another name for sequential
circuits. Finite refers to the fact that the number of states
the circuit can assume if finite
• A synchronous clocked FSM changes state only when
a triggering edge (or tick) occurs on the clock signal
 Clocked synchronous FSM structure
• States: determined by possible values in sequential storage
elements
• Transitions: change of state
• Clock: controls when state can change by controlling storage
elements
Inputs
Combinational
Outputs
Logic

Current State Next State

or
State
Clock

Storage Elements
 FSM Types
• There are two main types of FSMs
– Mealy (output is function of state and inputs)
– Moore (output is only function of state)
 Mealy machine

Next state = F1(current state, inputs)

Output = G1(current state, inputs)
Mealy state graph
Mealy state table

Present state Input Next state output

A B W Z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 1 0 1

0 1 1 0 1 0

1 0 0 0 0 0

1 0 1 0 0 1

1 1 0 x x 0

1 1 1 x x 0
Mealy maps
Mealy circuit diagram
 Moore machine

Next state = F2(current state, inputs)

Output = G2(current state)
Moore state graph:
Moore state table
Present state Input Next state output

A B W Z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 1 0 0

0 1 1 0 1 0

1 0 0 0 0 1

1 0 1 0 0 1

1 1 0 x x 0

1 1 1 x x 0
Moore maps
Moore circuit diagram:
 Comparison of Mealy and Moore FSM
• Mealy machines have less states
– outputs are on transitions (n2) rather than states (n)
• Moore machines are safer to use
– outputs change at clock edge (always one cycle later)
– in Mealy machines, input change can cause output change
as soon as logic is done – a big problem when two
machines are interconnected – asynchronous feedback
may occur if one isn’t careful
• Mealy machines react faster to inputs
– react in same cycle – don't need to wait for clock
– outputs may be considerably shorter than the clock cycle
– in Moore machines, more logic may be necessary to
decode state
into outputs – there may be more gate delays after clock
edge
 Finite state machine
• A FSM is an abstract model describing the
synchronous sequential machine.
• FSM design involves drawing state diagram
for the problem which is also known as word
problem.
• One state diagram is drawn, the next steps
involves reduction, state assignments and its
realization or design.
 Some examples of FSM
• Positive transition i.e. system
detectorgives output 1, whenever the
which
inputs changes
system to the from 0 to 1.
• Vending machine problems
• Serial Adder
• Serial Code Converters (BCD to
Excess-3)
• TLC( Traffic Light Controller)
• Sequence detectors
 Positive transition detector
• Suppose we have to design a sequential
system which is having one serial input IN
and will produce output OUT=1 whenever
input IN changes from 0 to 1. Input is
received one bit per cycle.
Step 1: Understand the problem
Step 2: Draw state diagram
Step3: reduction , state assignments and
design
• Step 1: The system is to have one input line
and one output line. Since the possible
transitions can 0 to 1 and 1 to 0, so we can
assume that we have only two state. Out of
these two state one state will represent that
current input is 1 and other state will represent
current input as 0.
• Step 2: Draw state diagram
• Step 3: No reduction needed.
• Step 4: State Assignments: Since we have only
two states, so we need only one bit to code the two
states.
In our case lets assign 0 to state Zero and 1 to state One.
• Step 5: Designs the circuit diagram
for this form state table as shown below.
Present state Input (IN) Next state Output (OUT) DA
QD
QD+1
0 0 0 0 0
0 1 1 1 1
1 0 0 0 0
1 1 1 0 1

Forming K – Map for DA and OUT we have

QD 0 1
QD 0 1
IN
IN
0 0 0 0 0 0

1 1 0 1 1 1

OUT=Q’D.IN DA= IN
• Circuit Diagram:
 Vending Machine Problem
• The vending machine delivers package of
gum after receiving minimum of 15 cents
of coin. The machine has a single slot that
accepts 10 cent coin or 5 cent coin one at
a time. A mechanical sensor indicates
whether 10 cent coin or 5 cent coin have
been inserted.
• Step 1: Understand problem
Assuming that sensor gives two outputs which
sense the coins. Lets take T signal for 10 cent
coin and F signal for 5.

As per given condition the gum is delivered

only when the coin inserted is minimum 15.
• There is 5 possible best way of getting 15 cent
minimum.

1. 5>5>5 ( 3 continuous 5 cent coin)

2. 5 > 10 (5 cent follows with 10 cent

coin)

3. 10 > 5 (10 cent follows with 5 cent

coin)

4. 10 > 10 (2 continuous 10 cent coin)

5. 5 > 5 > 10 (2 continuous 5 cent coin

follows
• Since once a package is delivered, the
machine should be in initial state for the
next customer.
• Also T=1 indicates 10 cent coin and
F=1 indicates 5 cent coin.
• We can’t have T=1 and F=1 at a
same time.
• Lets start drawing state diagram.
 Step 2: State Diagram
• Initially we will start with the state where nothing is
being sensed i.e. T=0 and F=0.
• The system will be in the initial state until T or F is
not 1. Once T or F is detected we can start with
states. If T=1 means 10 cent coin is being
received so this will be indicated by state S1. If
initially F=1 means 5 cent coin is received, so we
will indicate this as state S2.
• After S1, if T=1 means (case 4 ) i.e. our condition
is satisfied and package will be delivered so it will
be indicated by state SOPEN.
Step 3: State Reduction
• The details techniques for the state
reduction will be discussed later.
• Here we can directly draw the reduced
state diagram by care full observations.
5 cent coin follows by 10 cent coin will be
having same state when 10 cent coin
follows by 5 cent coin.
Similarly 10 cent coin state received from
starting state is equivalent to two
consecutive 5 cent coin.
Reduced state diagram
 State Assignments and design
Present State T F Next State Output COMMENT
Q0 Q1 Q0 Q1 Z

00 0 0 00 0 NO CHANGE
00 0 1 01 0 STATE 01
00 1 0 10 0 STATE 10
00 1 1 XX 0 NOT ALLOW STATE
01 0 0 01 0 NO CHANGE
01 0 1 10 0 STATE 10
01 1 0 11 1 STATE 11
01 1 1 XX 0 NOT ALLOW STATE
10 0 0 10 0 NO CHANGE
10 0 1 11 1 STATE 11
10 1 0 11 1 STATE 11
10 1 1 XX 0 NOT ALLOW STATE
11 0 0 00 0 TO RESET
11 0 1 00 0 TO RESET
11 1 0 00 0 TO RESET

11 1 1 00 0 TO RESET
 FSM for serial adder
• Suppose we have to add two inputs X and Y
where each bits of the inputs are coming
serially as shown below
 State Diagram for serial adder
• Since carry generated from first bit addition
must be added with the next bits, so care must
be taken.
• Lets we have two states A,B. State A indicating
carry=0 and the state B ,indicating carry=1.
 State table, state assignment
Present state Inputs Next state Output Present state Next state Output DQ
X (Sum) Inputs QN Y (Sum)
X QN+1
Y
A 0 0 A 0 0 0 0 0 0 0

A 0 1 A 1 0 0 1 0 1 0

A 1 0 A 1 0 1 0 0 1 0

A 1 1 B 0 0 1 1 1 0 1

B 0 0 A 1 1 0 0 0 1 0

B 0 1 B 0 1 0 1 1 0 1

B 1 0 B 0 1 1 0 1 0 1

B 1 1 B 1 1 1 1 1 1 1

a. State Table b. State Table after state assignment

• K-Maps and circuit design
K-Map for DQ=XY +XQN+YQN K-Map for sum=
XΘYΘQN
XY 00 01 11 10
XY 00 01 11 QN
QN 10
Where
0 Θ0 is Exor
1 0operation.
1
0 0 0 1 0

1 0 1 1 1 1 1 0 1 0
Simplified Presentation
 Serial code converters
• Binary to Gray code converter
• Gary to binary code converter( self)
• BCD to Excess-3 code converters ( Home
Assignment)
 Binary to Gray code converter
• In these type of system, input bit stream is
coming serially and output is also expected
serially.
• Here we have to use the truth table of
converter wisely.
 1. Whenever MSB is 0 corresponding
Binary Gray
Gary code value is 0 and when it’s
X2 X1 X0 Y2 Y1 Y0 1 the Gray code is 1.
2. Whenever the second bit, after 0
0 0 0 0 0 0 0 MSB ,is 0 then the corresponding
Gary code is 0 else its 1.
0 0 1 0 0 1
1
3. Whenever the second bit, after 1
0 1 0 0 1 1
2 MSB ,is 0 then the corresponding
0 1 1 0 1 0
Gary code is 1 else its 0.
3
4. Whenever the last bit, after 00 ,is 0
1 0 0 1 1 0
4 then the corresponding Gary code
1 0 1 1 1 1 is 0 else its 1.
5
1 1 0 1 0 1
5. Whenever the last bit, after 01 ,is 0
6 then the corresponding Gary code
1 1 1 1 0 0 is 1 else its 0.
7
6. Whenever the last bit, after 10 ,is 0
then the corresponding Gary code
is 0 else its 1.
7. Whenever the last bit, after 11 ,is 0
then the corresponding Gary code
is 1 else its 0.
• Draw State diagram using the state
table given in the previous slide
• Then the appropriate state
using and K-Map realization ,
assignment
design the system.
 Sequence Detector
• This is special type of systems which is used
whenever we need to check a particular pattern
in the input sequence
• Suppose input to the system is serial and we
have to design the system such that whenever
“101” is detected in the input, output will be 1.
INPUT 10010001001010100
: OUTPUT 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0

:
• There are two types of sequence detector.
(a) overlapping sequence detector
(b) non-overlapping sequence detector

In (a), we consider the input bit which may be common or

overlapping while deciding a pattern or desired sequence
in the input bit stream.

Let’s take example of sequence detector for 101. If input bit

sequence is 01010101…. , then output expected is
00010101 since when fourth bit is received , pattern 101
is received first time and output is available.

After that if two bits received are 0 , 1 , then the 1 that is

already there while forming pattern of 1 0 1 for the first
time will again form patter along with the two bit 0 ,1. so
output will be 1 again on 6th input bit, i.e the 1 in the 4th
location in the input is common in both 101 pattern
before and after this 1.
In (b) we need not to consider the input under
overlapping condition ie for obtaining desired
sequence, a input bits can not be considered more
then once.

How to draw state diagram for sequence detector

The input to the system is serially. Lets input is X and
output is Z. 101, sequence detector means out Z=1
whenever in the input stream X, we have 101
pattern ie for 01010101…. , as input stream , then
output Z expected is 00010101…….
 State diagram

S0- intial state

S1-1 101-seuence
S2-10
Non Overlapping Sequence Detector
• In non overlapping type of sequence detector, output will
be decided once the desired pattern is received and no
output will be there for any other pattern.
Let draw non-overlapping 101 sequence detector. While
drawing state diagram for non overlapping type of system,
it’s very easy to draw the state diagram since here each
bit is being treated independently as non overlapping. As
in the case of 101 detector, for input stream:
1001100101010101010……
Output will be : 0000000000010000010….
Chose a pair of three bits and searching for 101.
If 101 received then output is 1 otherwise output is
zero.
EXAMPLE: Draw state diagram for 3 bit palindrome checker i.e. a system
is taking input bit serially and output will be 1 when the three bits form a
palindrome sequence.