ANJUMAN COLLEGE OF ENGINEERING &

TECHNOLOGY
Department of Computer Science & Engineering

Chapter 1
Part II. Basic Processing Unit

Prof.Imteyaz Shahzad
Syllabus:
 UNIT I BASIC STRUCTURE OF COMPUTERS:
Functional units, Von Neumann Architecture, Basic operational concepts, Bus
structures Addressing modes, Subroutines: parameter passing, Instruction
formats: Three- address Instructions, Two-address instructions, One- address
instructions, Zero-address instructions. BASIC PROCESSING UNIT: Bus
architecture, Execution of a complete instruction, sequencing of control
signals, Hardwired control, Micro-programmed Control, microinstruction
format.
 UNIT II ARITHMETIC:
Number representations and their operations, Addition and Subtraction with
signed-magnitude, Design of Fast Adders, Array multiplier, Signed
multiplication: Booth's Algorithm, Bit-pair recoding, Integer Division,
Floating-point Arithmetic operations, guard bits and rounding.
 UNIT III THE MEMORY SYSTEM:
Various technologies used in memory design, higher order memory design,
Memory hierarchy, Main memory, Auxiliary memory, Cache memory, cache
optimization techniques ,Memory interleaving, Virtual memory, Address
Space and Memory Space, Associative memory, Page table, Page Replacement
 UNIT IV INPUT/OUTPUT ORGANIZATION:
I/O mapped I/O and memory mapped I/O, Interrupts and Interrupts
handling mechanisms, vectored interrupts, Synchronous vs.
Asynchronous data transfer, Direct Memory Access COMPUTER
PERIPHERALS: I/O devices such as magnetic disk, magnetic tape, CD-
ROM systems.
 UNIT V RISC philosophy
pipelining, basic concepts in pipelining, delayed branch, branch
prediction, data dependency, influence of pipelining on instruction set
design, multiple execution units, performance considerations,
 UNIT VI. Introduction to multiprocessors:
Basic concepts in parallel processing, classification of parallel
architectures. Vector Processing, Array Processor, Literature review of
multi-core architecture
COURSE OUTCOMES:
Understand the basic components of a computer,
including CPU, memories, and input/output, and their
organization; understand the execution of complete instruction.
Perform mathematical operations on arithmetic and floating
point numbers.
Understand the cost performance tradeoff in designing memory
hierarchy and instruction sets.
Understand the I/O operation, interrupts, memory access by I/O
and study different peripherals.
Understand the basic concept of pipeline execution of an
operation.
Understand the basic concept of parallel processing and multi-
core processor architecture.
Prerequisites
What is?
Basic Operational Concept
Program Counter (PC)
Central Processing Unit (CPU)
Instruction Register (IR)
Memory Address Register (MAR)
Memory Data Register (MDR)
Fundamental Concepts
Processor fetches one instruction at a time and
perform the operation specified.
Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
Instruction Register (IR)
Executing an Instruction
Fetch the contents of the memory location pointed to
by the PC. The contents of this location are loaded
into the IR (fetch phase).
IR ← [[PC]]
Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
Carry out the actions specified by the instruction in
the IR (execution phase).
Single Bus Architecture

Fig:refer from Carl Hamacher page 413

 Execution of Instruction

Transfer a word of data from one processor register to

another or to the ALU.
Perform an arithmetic or a logic operation and store
the result in a processor register.
Fetch the contents of a given memory location and
load them into a processor register.
Store a word of data from a processor register into a
given memory location.
 Internal processor
bus

Register Transfers Ri
Riin

Riout

Yin

Constant 4

Select MUX

A B
ALU

Zin

Z out

Fig.:Input and output gating for the registers Fig:refer from Carl
Hamacher page 416
Performing an Arithmetic or Logic
Operation
 ALU gets the two operands from MUX and bus. The
result is temporarily stored in register Z.
 First operand is always send to Register Y and
Second is directly send to point B of ALU
 What is the sequence of operations to add the
contents of register R2 to those of R3 and store the
result in R4?
1. R2out, Yin
2. R3out, SelectY, Add, Zin
3. Zout, R4in
Execution of a Complete
Instruction
Add (R1), R2
Fetch the instruction(Instruction Fetch Phase)
Fetch the first operand (the contents of the memory
location Stored at R1)
Perform the addition
Load the result into R2
Execution of a Complete
Instruction
Add (R3), R1
Execution of Branch Instructions
A branch instruction replaces the contents of PC with
the branch target address, which is usually obtained
by adding an offset X given in the branch instruction.
The offset X is usually the difference between the
branch target address and the address immediately
following the branch instruction.
Conditional branch
Execution of Branch Instructions
Step Action

1 PCout , MAR in , Read, Select4, Add, Z in

2 Zout , PC in , Yin , WMF C
3 MDR out , IR in
4 Offset-field-of-IRout , Add, Z in
5 Z out , PCin , End

Figure Control sequence for an unconditional branch instruction.

Multiple-Bus Organization
Bus A Bus B Bus C

Incrementer

PC

Re gister
file

Constant 4

MUX
A

ALU R

Instruction
decoder

IR

MDR

MAR

Memory bus Address Fig:refer from Carl

data lines lines
Hamacher page 424

Fig:Three Bus Organization of the datapath.

Multiple-Bus Organization
 Add R1, R2, R3

Step Action

1 PCout , R=B, MAR in , Read, IncPC

2 WMFC
3 MDR outB , R=B, IR in
4 R1 outA , R2 outB , SelectA, Add, R3 in , End

Figure:Control sequence for the instruction. Add R1,R2,R3,

for the three-bus organization