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FPGA Based System Design: Engr. Rashid Farid Chishti Lecturer, Dee, Fet, Iiui Chishti@Iiu - Edu.Pk Week 10

The document discusses BCD to excess-3 code conversion and Manchester encoding. It provides details on converting a BCD decimal number to excess-3 code using a state machine and behavioral modeling. It also describes Manchester encoding and provides examples of converting NRZ to Manchester encoding using a Mealy state machine model.

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Inayat Khan
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35 views

FPGA Based System Design: Engr. Rashid Farid Chishti Lecturer, Dee, Fet, Iiui Chishti@Iiu - Edu.Pk Week 10

The document discusses BCD to excess-3 code conversion and Manchester encoding. It provides details on converting a BCD decimal number to excess-3 code using a state machine and behavioral modeling. It also describes Manchester encoding and provides examples of converting NRZ to Manchester encoding using a Mealy state machine model.

Uploaded by

Inayat Khan
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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FPGA Based System Design

ENGR. RASHID FARID CHISHTI


LECTURER,DEE, FET, IIUI
[email protected]

WEEK 10

BCD TO EXCESS 3 CONVERTER


MANCHESTER ENCODING

www.iiu.edu.pk Saturday, November 27, 2021


BCD to Excess-3 Code Converter
 A serially-transmitted BCD (8421 code) Decimal 8-4-2-1 Excess-3
word is to be converted into an Excess- Digit Code Code
(BCD)
3 code
0 0000 0011
 An Excess-3 code word is obtained by
1 0001 0100
adding 3 to the decimal value and
2 0010 0101
taking the binary equivalent.
 Excess-3 code is self-complementing 3 0011 0110
4 0100 0111
!(0011) = 1100 again an excess-3 code
5 0101 1000
!(0100) = 1011
6 0110 1001
7 0111 1010
8 1000 1011
9 1001 1100

www.iiu.edu.pk 2 Saturday, November 27, 2021


Serial BCD to Excess-3 Code Converter

www.iiu.edu.pk 3 Saturday, November 27, 2021


Mealy Model State Machine
reset

Decimal BCD Excess-3


S0
Digit Code Code
0 0000 0011 1/0
0/1
1 0001 0100
2 0010 0101 S1 S4
1/0
3 0011 0110 0/1 0/0 1/1
1/1 0/0
4 0100 0111 0/1
5 0101 1000 S2 S5
6 0110 1001 0/1

7 0111 1010 0/0 1/1 1/0

8 1000 1011
S3 S6
9 1001 1100

www.iiu.edu.pk 4 Saturday, November 27, 2021


Behavioral Modeling
module BCD_to_Excess_3 (y, x, pstate, clk, reset);
output y, pstate; input x, clk, reset;
parameter S0 = 3'd0, S1 = 3'd1, S2 = 3'd2, S3 = 3'd3, S4 = 3'd4, S5 = 3'd5, S6 = 3'd6;
reg[2: 0] pstate, nxtstate; reg y;
always @ (posedge clk or negedge reset)
if (reset== 0) pstate <= S0; else pstate <= nxtstate;
always @ (pstate or x) begin
case (pstate)
S0: if (x) begin nxtstate = S4; y = 0; end
else begin nxtstate = S1; y = 1; end
S1: if (x) begin nxtstate = S5; y = 0; end
else begin nxtstate = S2; y = 1; end
S2: begin nxtstate = S3; y = x; end
S3: begin nxtstate = S0; y = x; end
S4: begin nxtstate = S5; y = x; end
S5: if (x) begin nxtstate = S6; y = 0; end
else begin nxtstate = S3; y = 1; end
S6: begin nxtstate = S0; y = 1; end
default: begin nxtstate = 3'dx; y = 1'bx; end
endcase end endmodule
www.iiu.edu.pk 5 Saturday, November 27, 2021
Test Bench

reset

module Test_BCD_to_Excess3; S0

1/0
wire y; wire [2:0]pstate; reg x, clk, reset; 0/1
BCD_to_Excess_3 BE1 (y, x, pstate, clk, reset);
S1 S4
initial begin reset = 1; 1/0
#7 reset = 0; #3 reset = 1; 0/1 0/0 1/1
1/1 0/0
end
0/1
initial begin clk = 0;
repeat (20) #5 clk = ~clk; S2 S5
end 0/1
initial begin x = 1; 0/0 1/1 1/0
repeat (10) #10 x = ~ x;
end
S3 S6
endmodule

www.iiu.edu.pk 6 Saturday, November 27, 2021


Manchester Encoding

 Each bit is transmitted in a fixed time (the "period").


 A 0 is expressed by a low-to-high transition, a 1 by high-to-low transition.
 The transitions which signify 0 or 1 occur at the midpoint of a period.
 Transitions at the start of a period are overhead and don't signify data.
 Manchester coding is widely used in Ethernet, RFID and Near Field Communication.

1/1 0/0

S1 S0 S2

1/0 0/1
www.iiu.edu.pk 7 Saturday, November 27, 2021
Manchester Encoding
module NRZ_2_Manchester_Mealy (B_out, state, B_in, clock, reset_b);
output B_out; input B_in; input clock, reset_b; output state;
reg [1: 0] state, next_state; reg B_out;
parameter S0 = 0, S1 = 1, S2 = 2, dont_care_state = 2'bx, dont_care_out = 1'bx;
always @ (negedge clock or negedge reset_b)
if (reset_b == 0) state <= S0;
else state <= next_state; 1/1 0/0
always @ (state or B_in ) begin
S1 S0 S2
B_out = 0;
case (state) 1/0 0/1
S0: if (B_in == 0) begin next_state = S2; B_out = 0; end
else if (B_in == 1) begin next_state = S1; B_out = 1; end
S1: begin next_state = S0; B_out = 0; end
S2: begin next_state = S0; B_out = 1; end
default: begin next_state = dont_care_state;
B_out = dont_care_out; end
endcase
end
endmodule

www.iiu.edu.pk 8 Saturday, November 27, 2021


Manchester Encoding Test Bench

module test_NRZ_2_Manchester_Mealy;
wire B_out; reg B_in, clk, rst; wire [1:0] state; reg clk2;
NRZ_2_Manchester_Mealy (B_out, state, B_in, clk, rst); 1/1 0/0

S1 S0 S2

1/0 0/1
initial begin rst = 1; #7 rst = 0; #3 rst = 1; end
initial begin clk = 0;
repeat (20) #5 clk = ~clk; end
initial begin clk2 = 1;
repeat (10) #10 clk2 = ~clk2; end
initial begin B_in = 1;
repeat (3) #40 B_in = ~ B_in; end
endmodule
www.iiu.edu.pk 9 Saturday, November 27, 2021

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