Embedded Systems Design – 2

(ICE – NITT)

ARM Processors

Dr. N. Mathivanan
 Topics
• Features of ARM processors
• ARM architecture variants and professor families
• ARM7-TDMI internal architecture
• Register organization
• Pipelining
• Operating modes
• Exception handling
• ARM bus architecture
• Debug architecture
• Interface signals
 ARM Processors
• Advanced RISC Machine -
ARM Ltd. not a manufacturing Co., provides license to manufacturers
Used in high end applications involving complex computation
Hand held device, Robotic, Automation system, Consumer electronics

• Features
High performance, low power, small in size (ideal for embedded sys)
Large Register File, Small instruction set, Load-Store instructions,
Fixed length instructions, Conditional execution of instructions,
High code density, most instructions executable in single cycle,
32-bit in-line barrel shifter, built-in circuit for hardware debugging,
DSP enhanced instructions, Jazelle (Java byte code extn. 3 rd state),
TrustZone (SoC approach to security)
 ARM Architecture Variants (core), Processor Families
• Each family has its own instruction set, mem management, etc.
Architecture Processor
Processor Features Microcontroller
version Families
ARM7TDMI ARM720T Von Neumann,
LPC2100 series
(1995) ARM740T 3-stage pipeline
ARM v4T ARM920T
MMU, Harvard, SAM9G, LPC29xx,
ARM9TDMI ARM922T
5-stage pipeline LPC3xxx, STR9
ARM942T
ARM926EJ-S, MMU, DSP, Jazelle, SAM9XE
ARM9E
ARM946E-S, MPU, DSP
ARM v5TE, (1997)
ARM966HS MPU (optional), DSP  
ARM v5TEJ
ARM10E ARM1020E MMU, DSP  
(1999) ARM1026EJ-S MMU/MPU, DSP, Jazelle  

ARM1136J(F)-S MMU, TrustZone, DSP, Jazelle MSM7000, i.MX3x

ARM1156T2(F)-S MPU, DSP  

ARM11
ARM v6 ARM1176JZ(F)-S, MMU, TrustZone, DSP, Jazelle BCM2835
(2003)
MMU, Multiprocessor cache
ARM11 MP core  
support, DSP, Jazelle
Architecture Processor
Processor Features Microcontroller
version Families

LPC1200, 1100 series

Cortex-M0 NVIC
STM32F0x0, x1, x2
ARM v6-M Cortex

Cortex-M1 FPGA TCM Interface, NVIC STM32F1, F2, L1, W

ST32F512-M, LPC1300,
ARM v7-M Cortex Cortex-M3 MPU (optional), NVIC
1700, 1800

STA1095, SAM4L,
Cortex-R4 MPU, DSP
SAM4N, SAM4S

ARM v7-R Cortex

SAM4C, SAM4E,
Cortex-R4F MPU, DSP, Floating Point LPC40xx, 43xx, STM32
F3, F4

MMU, Trust Zone, DSP,

Cortex-A8 Freescale i.MX5X
Jazelle, Neon, Floating Point
ARM v7-A Cortex
MMU, Trust Zone,
Cortex-A9 Multiprocessor, DSP, Jazelle, Freescale i.MX6QP
Neon, Floating Point
 ARM Nomenclature
• A R M x y z T D M I E J F S (Example: ARM7-TDMI-S)
x – Series

y – MMU

z – Cache

T – Thumb

D – Debugger

M – Multiplier

I – Embedded In-Circuit Emulator (ICE) macrocell

E – Enhanced Instructions for DSP

J – JAVA acceleration by Jazelle

F – Floating-point

S – Synthesizable version
 ARM7-TDMI – Internal Architecture
A d d re ss B u s
A [3 1 :0 ]

• Von Neumann architecture

A d d r e s s R e g is t e r

In cre m e n te r B u s
• Data bus – 32-bit

PC Bus
A d d re ss

Address bus – 32-bit

In c r e m e n t e r
•

I n s t r u c ti o n D e c o d e r a n d
R e g is t e r B a n k

Addressable memory space – 4 GB

( 3 1 x 3 2 - b it r e g is t e r s )
( 6 s t a t u s r e g is t e r s )

L o g ic C o n t r o l
• Register bank – (31+6) 32-bit regs. 32 x 8
m u l ti p l i e r

• In-line barrel shifter

ALU Bus

A Bus

B Bus
• Multiplier B a r r e l S h i ft e r

• ALU ALU

• Incrementer

• Address register D a t a O u t R e g is t e r D a t a I n R e g is t e r

• Instruction decoder & control logic D a t a B u s D [3 1 :0 ]

 Register Organization
31 gen. purpose registers. U se r M ode

Only 16 regs accessible r0

r1
15 registers are hidden
r2

Named as r0 – r15 r3

r4
r13,r14, r15 are SP, LR, PC
r5
8-bit/16-bit/32-bit data can be r6
B a n k e d R e g is te rs
F IQ
read/write r7

r8 r 8 _ fi q

6 status registers r9 r 9 _ fi q

r1 0
Only 1 is accessible r 1 0 _ fi q

r1 1 r 1 1 _ fi q
Named as CPSR, SPSR r1 2
IR Q Undef A b o rt SV C
r 1 2 _ fi q

Contains flags, control bits r1 3 _ s p r 1 3 _ fi q r 1 3 _ ir q r1 3 _ u n d r1 3 _ ab t r1 3 _ svc

r1 4 _ lr r 1 4 _ fi q r 1 4 _ ir q r1 4 _ u n d r1 4 _ ab t r1 4 _ svc

r1 5 _ p c
Register bank has
2 read and 1 write port and CPSR
S P S R _ fi q S P S R _ ir q SPSR_ und SP SR_ ab t SP SR _ svc
1 read and 1 write port for PC
• Bit definitions of Program Status registers
B31 B24 B23 B16 B15 B8 B7 B0
N Z C V I F T M 4 M 3 M 2 M 1 M 0

M ode
O v e r fl o w
C arry T h u m b S t a t e F la g
Ze ro F IQ In t e r r u p t M a s k
N e g a ti v e IR Q I n t e r r u p t M a s k

• Barrel shifter

Combinational logic circuit

Shifts left/right any no. of bits position in one cycle

Preprocess one of data from source reg. before passed to ALU

• Multiplier

32-bit x 8-bit with early termination, Booth Algorithm

32-bit x 32-bit in 5 cycles

Non M type multiplies in 32x2-bit and for 32-bitx32-bit - 17 cycles

 Review Questions
1. What is the size of address and data busses in ARM7 processor?
2. What is the size of memory space ARM7 processor can address?
3. List the features of ARM processors.
4. What does ‘TDMI-S’ in ARM7-TDMI-S refer to?
5. What are the special functions of r13, r14 and r15 registers?
6. What are special features of multiplier block in ARM7 processor?
7. What are CPSR and SPSR?
8. What are the functions of control bits of program status register?
9. What is the purpose and feature of barrel shifter?
10. Describe the internal architecture of ARM7 processor