ECEG-4221 VLSI Design

Addis Ababa Institute of Technology (AAIT) Department of Electrical and

Computer Engineering
Learning Outcomes

 At the end of the lecture, students should get

familiarized with :
 PLD.
 PLA.
 PAL.
 ROM.
 CPLD.
 FPGA.

AAIT, Department of
Electrical and Computer 2 Nebyu Yonas Sutri
Engineering
Programmable Logic Devices (PLD)
 When combinational logic gets large, it becomes
impractical to implement using discrete devices.
 An alternative way to an Application Specific Integrated
Circuit (ASIC) is a programmable logic device.
 There are many types of programmable logic to
choose from, each with advantages/disadvantages.
 PLA
 PAL
 CPLD
 FPGA
 The type of programmable device we target can
influences how we minimize/synthesize our logic.
AAIT, Department of
Electrical and Computer 3 Nebyu Yonas Sutri
Engineering
Programmable Logic Devices (PLD)
 It is possible to manufacture chips that contain
relatively large amounts of logic circuitry with a
structure that is not fixed.
 Such chips were first introduced in the 1970s and are
called programmable logic devices (PLDs).
 A PLD is a general-purpose chip for implementing logic
circuitry. It contains a collection of logic circuit
elements that can be customized in different ways.
 A PLD can be viewed as a “black box” that contains
logic gates and programmable switches.

AAIT, Department of
Electrical and Computer 4 Nebyu Yonas Sutri
Engineering
PLD as Black Box

Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches

AAIT, Department of
Electrical and Computer 5 Nebyu Yonas Sutri
Engineering
 Programmable Logic Array (PLA)
 A PLA is a 2-level AND-OR configuration that implements
SOP expressions.
 A PLA has:
 n inputs
 m outputs
 p product terms.
 Inputs are initially buffered and inverted to always create X
and X’ literals.
 Fuses (or reconfigurable switches) are used to selectively
connect the literals to the AND level.
 Fuses are again used to decide which product terms are
connected to the OR level.

AAIT, Department of
Electrical and Computer 6 Nebyu Yonas Sutri
Engineering
Programmable Logic Array (PLA)
x 1 x2 xn

 Use to implement
circuits in SOP form.
Input buffers
and
inverters
 The connections in
the AND plane are x 1 x1 xn x n
programmable.
P1

 The connections in AND plane OR plane

the OR plane are Pk
programmable

f1 fm
AAIT, Department of
Electrical and Computer 7 Nebyu Yonas Sutri
Engineering
 Gate Level Version of PLA x1 x2 x3

f1 = x1x2+x1x3'+x1'x2'x3 Programmable
connections
f2 = x1x2+x1'x2'x3+x1x3 OR plane
P1

 Signals that are

connected to the P
2
AND & OR gates
are indicated with a
wavy lines. P3
 Signal that is not
connected to the P
4
gate is shown with a
broken line.
AND plane

f1 f2
AAIT, Department of
Electrical and Computer 8 Nebyu Yonas Sutri
Engineering
 Customary Schematic of a PLA
x1 x2 x3

OR plane
f1 = x1x2+x1x3'+x1'x2'x3 P1

f2 = x1x2+x1'x2'x3+x1x3
P2

 X marks the
P3
connections left
in place after
programming. P4

AND plane

f1 f2

AAIT, Department of
Electrical and Computer 9 Nebyu Yonas Sutri
Engineering
Example of a simple PLA
2-input, 2-output, 2-product term PLA
The X’s represent where the fuses can be left connected or blown.

AAIT, Department of
Electrical and Computer 10 Nebyu Yonas Sutri
Engineering
Limitations of PLAs
 PLAs come in various sizes.
 Typical size is 16 inputs, 32 product terms, 8 outputs.
 Each AND gate has large fan-in  This limits the number of inputs
that can be provided in a PLA.
 16 inputs  Lots of possible input combinations; only 32 permitted
(since 32 AND gates) in a typical PLA.

 32 AND terms permitted  large fan-in for OR gates as well

 This makes PLAs slower and slightly more expensive than
some alternatives to be discussed shortly.
 8 outputs  Could have been more!

AAIT, Department of
Electrical and Computer 11 Nebyu Yonas Sutri
Engineering
Programmable Array Logic (PAL)
 A PAL is an extension of a PLA but uses a fixed OR
stage instead of a programmable one.
 Since 0’s going into an OR have no effect, this is
possible.
 Because they are simpler to manufacture, and thus
less expensive than PLAs, and offer better
performance, PALs have become popular in practical
applications
 A PAL also has some additional functionalities
 Output enables.
 Output feed back.
AAIT, Department of
Electrical and Computer 12 Nebyu Yonas Sutri
Engineering
Programmable Array Logic (PAL)
x 1 x2 xn

 Also used to implement

circuits in SOP form Input buffers
and
inverters fixed connections
 The connections in
x 1 x1 xn x n
the AND plane are
programmable
P1

 The connections in AND plane OR plane

Pk
the OR plane are
NOT programmable
f1 fm
AAIT, Department of
Electrical and Computer 13 Nebyu Yonas Sutri
Engineering
 Example Schematic of a PAL
x1 x2 x3

P1

f1 = x1x2x3'+x1'x2x3 f1
P2
f2 = x1'x2'+x1x2x3
P3

f2
P4

AND plane
AAIT, Department of
Electrical and Computer 14 Nebyu Yonas Sutri
Engineering
Comparing PALs and PLAs
 PALs have the same limitations as PLAs (small
number of allowed AND terms) plus they have a fixed
OR plane  less flexibility than PLAs.

 PALs are simpler to manufacture, cheaper, and faster

(better performance).

 PALs also often have extra circuitry connected to the

output of each OR gate and additional functionality.

AAIT, Department of
Electrical and Computer 15 Nebyu Yonas Sutri
Engineering
Programming SPLDs
 PLAs, PALs, and ROMs are also called
SPLDs – Simple Programmable Logic Devices.

 SPLDs must be programmed so that the switches are

in the correct places.
 CAD tools are usually used to do this
 A fuse map is created by the CAD tool and then that map is
downloaded to the device via a special programming unit.

 There are two basic types of programming techniques

 Removable sockets on a PCB.
 In system programming (ISP) on a PCB.
 This approach is not very common for PLAs and PALs but it is
quite common for more complex PLDs.

AAIT, Department of
Electrical and Computer 16 Nebyu Yonas Sutri
Engineering
SPLD Programming Unit

 The SPLD is removed from the PCB, placed into the

unit and programmed there

AAIT, Department of
Electrical and Computer 17 Nebyu Yonas Sutri
Engineering
Removable SPLD Socket Package
 PLCC (plastic-leaded chip carrier)

PLCC socket soldered to

the PCB

o ard
u itb
c
d cir
nte
Pri

AAIT, Department of
Electrical and Computer 18 Nebyu Yonas Sutri
Engineering
In System Programming (ISP)
 Used when the SPLD cannot be removed from the
PCB.
 A special cable and PCB connection are required to
program the SPLD from an attached computer.
 Very common approach in programming more
complex PLDs like CPLDs, FPGAs, etc.

AAIT, Department of
Electrical and Computer 19 Nebyu Yonas Sutri
Engineering
CPLD
 Complex Programmable Logic Devices (CPLD)
 SPLDs (PLA, PAL) are limited in size due to the small
number of input and output pins and the limited
number of product terms
 Combined number of inputs + outputs < 32 or so.
 CPLDs contain multiple circuit blocks on a single chip
 Each block is like a PAL: PAL-like block
 Connections are provided between PAL-like blocks via an
interconnection network that is programmable.
 Each block is connected to an I/O block as well.
 Commercial CPLDs range in size from only 2 PAL-like
blocks to more than 100 PAL like blocks.

AAIT, Department of
Electrical and Computer 20 Nebyu Yonas Sutri
Engineering
Structure of a CPLD
I/O block

I/O block
PAL-like PAL-like
block block

Interconnection wires
I/O block

I/O block
PAL-like PAL-like
block block

AAIT, Department of
Electrical and Computer 21 Nebyu Yonas Sutri
Engineering
Programming a CPLD
 CPLDs have many pins – large ones have > 200
 Removal of CPLD from a PCB is difficult without breaking the
pins.
 Use ISP (in system programming) to program the CPLD.
 JTAG (Joint Test Action Group) port used to connect the
CPLD to a computer.

AAIT, Department of
Electrical and Computer 22 Nebyu Yonas Sutri
Engineering
Example CPLD
 Use a CPLD to implement the function
 f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7

(from interconnection wires)

x1 x2 x3 x4 x5 x6 x7 unused

PAL-like block
0 1
0
f
D Q

AAIT, Department of
Electrical and Computer 23 Nebyu Yonas Sutri
Engineering
FPGA
 SPLDs and CPLDs are relatively small and useful for
simple logic devices.
 Up to about 20,000 gates.
 By modern standards, a logic circuit with 20,000 gates is not
large.
 Field Programmable Gate Arrays (FPGA) can handle
larger circuits.
 No AND/OR planes.
 Provide logic blocks, I/O blocks, and interconnection wires
and switches.
 Logic blocks provide functionality.
 Interconnection switches allow logic blocks to be connected to
each other and to the I/O pins.

AAIT, Department of
Electrical and Computer 24 Nebyu Yonas Sutri
Engineering
FPGA
 FPGA uses Re-configurable Logic Blocks.
 We set the config bits of this block to set its Boolean logic
function.
 The configuration is a Truth Table (or Look Up Table) of
functionality.

In1 config Out

Out 000 NOT(In1)
In2 001 NOT(In2)
010 OR
config 011 NOR
100 AND
101 NAND
110 XOR
111 XNOR

AAIT, Department of
Electrical and Computer 25 Nebyu Yonas Sutri
Engineering
 FPGA
 LUTs = Look Up Tables
- We can program the LUTs to be whatever type of gate is needed by the design
- There are a finite number of LUTs within a given FPGA (also called "resources")

 The LUTs are configured into an ARRAY on the silicon

- Array of LUT's = Array of Gates = Gate Array
In1 In1 In1
Out Out Out
In2 In2 In2

config config config

In1 In1 In1

Out Out Out
In2 In2 In2

config config config

In1 In1 In1

Out Out Out
In2 In2 In2

config config config

AAIT, Department of
Electrical and Computer 26 Nebyu Yonas Sutri
Engineering
FPGA
 Programmable Interconnect
- There are programmable interconnect switches that connect the LUTs

LUT X LUT X LUT

X X X X X

LUT X LUT X LUT

X X X X X

LUT X LUT X LUT

AAIT, Department of
Electrical and Computer 27 Nebyu Yonas Sutri
Engineering
FPGA
 Configuration
- We start with a Gate Level Schematic of our design (from synthesis)
- The FPGA LUTs are configured to implement Gates

LUT X LUT X LUT

X X X X X

LUT X LUT X LUT

X X X X X

LUT X LUT X LUT

AAIT, Department of
Electrical and Computer 28 Nebyu Yonas Sutri
Engineering
FPGA
 Configuration
- The interconnect switches are then programmed to implement the net connections

A INV X AND X LUT

B X X X X X Out

C INV X OR X LUT

X X X X X

LUT X LUT X LUT

AAIT, Department of
Electrical and Computer 29 Nebyu Yonas Sutri
Engineering
FPGA
 Configuration
- The LUT and Interconnect configuration is volatile (i.e., it goes away when power is removed)

- Since the programming is done by the user after fabrication, we call it "Field Programmable"

A INV X AND X LUT

B X X X X X Out

C INV X OR X LUT

X X X X X

LUT X LUT X LUT

- We now understand where Field Programmable Gate Array.

AAIT, Department of
Electrical and Computer 30 Nebyu Yonas Sutri
Engineering
Structure of an FPGA
I/O block

Interconnection
switch I/O block

I/O block
Logic block I/O block

AAIT, Department of
Electrical and Computer 31 Nebyu Yonas Sutri
Engineering
Programming an FPGA
 ISP method is used.

 LUTs contain volatile storage cells.

 None of the other PLD technologies are volatile.
 FPGA storage cells are loaded via a PROM when power is
first applied.

 The UP2 Education Board by Altera contains a JTAG

port, a MAX 7000 CPLD, and a FLEX 10K FPGA
 The MAX 7000 CPLD chip is EPM7128SLC84-7
 EPM7  MAX 7000 family; 128 macrocells; LC84  84 pin
PLCC package; 7  speed grade

AAIT, Department of
Electrical and Computer 32 Nebyu Yonas Sutri
Engineering
Example FPGA
 Use an FPGA with 2 input LUTS to implement the
function f = x1x2 + x2'x3 x 3 f

 f1 = x1x2
x1
 f2 = x2'x3
 f = f1 + f2 x1 0
0 f1
x2 0
1 f2
0 0
x2 x2 x3
1 0

f1 0
1 f
1
f2
1

AAIT, Department of
Electrical and Computer 33 Nebyu Yonas Sutri
Engineering
Example FPGA
 f = (x1x6' + x2x7)(x3 + x4x5)
x4 x5 x3 f

x1

x1 0 x4 0 x3 0
0 A 0 C 1 E
x6 x6 1 x5 0 C 1
1
0 1

x2

x2 0 A 0 D 0
0 B 1 D 0 f
x7 x7 0 1
B 1
0
E 1
1

AAIT, Department of
Electrical and Computer 34 Nebyu Yonas Sutri
Engineering
 Digital Logic Technology Tradeoffs

Full custom
VLSI design

ASICs
Speed / Density /
Complexity / Likely
Market Volume CPLDs
FPGAs

PLDs

Engineering cost / Time to develop

AAIT, Department of
Electrical and Computer 35 Nebyu Yonas Sutri
Engineering
ROM (Read Only Memory)
 Similar to a PLA structure but with a fully decoded
AND array.

 A ROM (Read Only Memory) has a fixed AND plane

and a programmable OR plane.

 Size of AND plane is 2n where n = number of input

pins.
 Has an AND gate for every possible minterm so that all input
combinations access a different AND gate.

 OR plane dictates function mapped by the ROM.

AAIT, Department of
Electrical and Computer 36 Nebyu Yonas Sutri
Engineering
ROM
 A ROM contains permanently or semipermanently
stored date, which can be read from the memory but
either cannot be changed at all of cannot be changed
without specialized equipment.

AAIT, Department of
Electrical and Computer 37 Nebyu Yonas Sutri
Engineering
 ROM
 Mask ROM made from either MOS or bipolar technology
and it is permanently programmed during manufacturing.
 PROM made from either MOS or bipolar technology and
they come from the manufacturer unprogrammed. Once
programmed by the customer they are like mask ROM.
 EPROM, UV EPROM and EEPROM are strictly based on
MOS technology and they are erasable devices with a
capability of reprogrammbility.

AAIT, Department of
Electrical and Computer 38 Nebyu Yonas Sutri
Engineering
End of DLD (ECEG-4221) Course!

AAIT, Department of
Electrical and Computer 39 Nebyu Yonas Sutri
Engineering