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Phase-Locked Loop Basics, PLL PLL Basics

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42 views

Phase-Locked Loop Basics, PLL PLL Basics

Uploaded by

nddnayan
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Phase-Locked Loop Basics, PLL

PLL Basics

A phase-locked loop (PLL) is a closed-loop frequency-control system based on the phase


difference between the input clock signal and the feedback clock signal of a controlled
oscillator. Figure 1 shows a simplified block diagram of the major components in a PLL. The
main blocks of the PLL are the phase frequency detector (PFD), charge pump, loop filter,
voltage controlled oscillator (VCO), and counters, such as a feedback counter (M), a pre-
scale counter (N), and post-scale counters(C).
PLLs in Altera® FPGAs align the rising edge of the reference input clock to a feedback
clock using the PFD. The falling edges are determined by the duty-cycle specified by
the user. The PFD detects the difference in phase and frequency between the
reference clock and feedback clock inputs and generates an “up” or “down” control
signal based on whether the feedback frequency is lagging or leading the reference
frequency. These “up” or “down” control signals determine whether the VCO needs
to operate at a higher or lower frequency, respectively.
The PFD outputs these “up” and “down” signals to a charge pump. If the charge
pump receives an up signal, current is driven into the loop filter. Conversely, if it
receives a down signal, current is drawn from the loop filter.
The loop filter converts these signals to a control voltage that is used to bias the VCO.
Based on the control voltage, the VCO oscillates at a higher or lower frequency,
which affects the phase and frequency of the feedback clock. If the PFD produces an
up signal, then the VCO frequency increases. A down signal decreases the VCO
frequency. The VCO stabilizes once the reference clock and the feedback clock have
the same phase and frequency. The loop filter filters out jitter by removing glitches
from the charge pump and preventing voltage over-shoot.
A divide counter (M) is inserted in the feedback loop to increase the VCO frequency
above the input reference frequency. VCO frequency (FVCO) is equal to (M) times the
input reference clock (FREF). The PFD input reference clock (FREF) is equal to the input
clock (FIN) divided by the pre-scale counter (N). Therefore, the feedback clock (F FB)
applied to one input of the PFD is locked to the FREF that is applied to the other input of
the PFD. The VCO output feeds post-scale counters which allow a number of
harmonically related frequencies to be produced within the PLL.
The output frequency of the PLL is equal to the VCO frequency (F VCO) divided by the
post-scale counter (C).
Phase-locked loops are widely used for synchronization purposes;
in space communications for coherent demodulation

threshold[disambiguation needed] extension, bit synchronization, and

symbol synchronization. Phase-locked loops can also be used to demodulate


frequency-modulated signals.

In radio transmitters, a PLL is used to synthesize new frequencies which are a


multiple of a reference frequency, with the same stability as the reference
frequency.

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