Chapter 4

•Cascade n full adder (FA) blocks to form a n-bit adder.

•Carries propagate or ripple through this cascade, n-bit ripple carry adder.

xn - 1
yn- 1 x1 y1 x0 y0

cn - 1
c1
cn FA FA FA c0

sn - 1
s1 s0
Most significant bit Least significant bit
(MSB) position (LSB) position

Carry-in c0 into the LSB position provides a convenient way to

perform subtraction.
 K n-bit numbers can be added by cascading k n-bit adders.

xk n - 1 yk n - 1 x2n - 1 y2n - 1
xn y n xn - y
1 n- 1
x0 y0

cn
n-bit n-bit n-bit c
c kn 0
adder adder adder

s s s s s s
kn - 1 k - 1 n 2n - 1 n n- 1 0

Each n-bit adder forms a block, so this is cascading of blocks.

Carries ripple or propagate through blocks, Blocked Ripple Carry Adder
 y y y
n- 1 1 0
Add/Sub
control

x x x
n- 1 1 0

c n-bit adder
n c
0

s s s
n- 1 1 0

•Add/sub control = 0, addition.

•Add/sub control = 1, subtraction.
Recall the equations:

si  xi  yi  ci
ci 1  xi yi  xi ci  yi ci
Second equation can be written as:

ci 1  xi yi  ( xi  yi )ci
We can write:
ci 1  Gi  Pi ci
where Gi  xi yi and Pi  xi  yi

•Gi is called generate function and Pi is called propagate function

•Gi and Pi are computed only from xi and yi and not ci, thus they can
be computed in one gate delay after X and Y are applied to the
inputs of an n-bit adder.
 ci 1  Gi  Pi ci
ci  Gi 1  Pi 1ci 1
 ci1  Gi  Pi (Gi 1  Pi 1ci 1 )
continuing
 ci1  Gi  Pi (Gi 1  Pi 1 (Gi  2  Pi 2 ci 2 ))
until
ci1  Gi  PiGi 1  Pi Pi1 Gi 2  ..  Pi Pi 1 ..P1G0  Pi Pi 1 ...P0 c 0
•All carries can be obtained 3 gate delays after X, Y and c0 are applied.
-One gate delay for Pi and Gi
-Two gate delays in the AND-OR circuit for ci+1
•All sums can be obtained 1 gate delay after the carries are
computed.
•Independent of n, n-bit addition requires only 4 gate delays.
•This is called Carry Lookahead adder.
 x y x y x y x y
3 3 2 2 1 1 0 0

c4
c
3
c
2
c
1
. c
4-bit
carry-lookahead
B cell B cell B cell B cell 0

adder
s s s s
3 2 1 0

G3 P3 G2 P2 G P G P
1 1 0 0

Carry-lookahead logic
xi yi

. .
. c
i

B-cell for a single stage

B cell

Gi P i
si
Carry lookahead adder (contd..)
Performing n-bit addition in 4 gate delays independent of n
is good only theoretically because of fan-in constraints.

ci1  Gi  PiGi 1  Pi Pi1 Gi 2  ..  Pi Pi 1 ..P1G0  Pi Pi 1 ...P0 c0

Last AND gate and OR gate require a fan-in of (n+1) for a n-
bit adder.
 For a 4-bit adder (n=4) fan-in of 5 is required.
 Practical limit for most gates.
In order to add operands longer than 4 bits, we can cascade
4-bit Carry-Lookahead adders. Cascade of Carry-Lookahead
adders is called Blocked Carry-Lookahead adder.
Product of 2 n-bit numbers is at most a 2n-bit number.
Unsigned multiplication can be viewed as addition of shifted
versions of the multiplicand.
 Multiplication of unsigned
numbers (contd..)
We added the partial products at end.
 Alternative would be to add the partial products at each stage.

Rules to implement multiplication are:

 If the ith bit of the multiplier is 1, shift the multiplicand and add the
shifted multiplicand to the current value of the partial product.
 Hand over the partial product to the next stage
 Value of the partial product at the start stage is 0.
Sequential multiplication
Recall the rule for generating partial products:
 If the ith bit of the multiplier is 1, add the appropriately shifted multiplicand
to the current partial product.
 Multiplicand has been shifted left when added to the partial product.

However, adding a left-shifted multiplicand to an

unshifted partial product is equivalent to adding an
unshifted multiplicand to a right-shifted partial
product.
 M
1 1 0 1
Initial configuration
0 0 0 0 0 1 0 1 1
C A Q
0 1 1 0 1 1 0 1 1 Add
Shift First cycle
0 0 1 1 0 1 1 0 1

1 0 0 1 1 1 1 0 1 Add
Shift Second cycle
0 1 0 0 1 1 1 1 0

0 1 0 0 1 1 1 1 0 No add
Shift Third cycle
0 0 1 0 0 1 1 1 1

1 0 0 0 1 1 1 1 1 Add
Shift Fourth cycle
0 1 0 0 0 1 1 1 1

Product
Signed Multiplication
 Considering 2’s-complement signed operands, what will happen to (-
13)(+11) if following the same method of unsigned multiplication?

1 0 0 1 1  - 13
0 1 0 1 1 ( + 11)

1 1 1 1 1 1 0 0 1 1

1 1 1 1 1 0 0 1 1
Sign extension is
shown in blue 0 0 0 0 0 0 0 0

1 1 1 0 0 1 1

0 0 0 0 0 0

1 1 0 1 1 1 0 0 0 1  - 143

Sign extension of negative multiplicand.

Signed Multiplication
For a negative multiplier, a straightforward solution is
to form the 2’s-complement of both the multiplier and
the multiplicand and proceed as in the case of a
positive multiplier.
This is possible because complementation of both
operands does not change the value or the sign of the
product.
A technique that works equally well for both negative
and positive multipliers – Booth algorithm.
Booth Algorithm
Consider in a multiplication, the multiplier is positive
0011110, how many appropriately shifted versions of
the multiplicand are added in a standard procedure?

0 1 0 1 1 0 1
0 0 +1 +1 + 1+1 0
0 0 0 0 0 0 0
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0
Booth Algorithm
Since 0011110 = 0100000 – 0000010, if we use the
expression to the right, what will happen?

0 1 0 1 1 0 1
0 +1 0 0 0-1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 0 1 0 0 1 1 2's complement of
0 0 0 0 0 0 0 0 0 0 0 0 the multiplicand
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 0 1
0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0
Booth Algorithm
 In general, in the Booth scheme, -1 times the shifted multiplicand is
selected when moving from 0 to 1, and +1 times the shifted
multiplicand is selected when moving from 1 to 0, as the multiplier
is scanned from right to left.
0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0

0 +1 -1 +1 0 - 1 0 +1 0 0 - 1 +1 - 1 + 1 0 - 1 0 0

Booth recoding of a multiplier.

Booth Algorithm
0 1 1 0 1 ( + 13) 0 1 1 0 1
X1 1 0 1 0 - 6 0 - 1 +1 - 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 0  - 78

Booth multiplication with a negative multiplier.

Booth Algorithm
Multiplier
V ersion of multiplicand
selected by biti
Bit i Bit i -1

0 0 0 XM
0 1 + 1 XM
1 0  1 XM
1 1 0 XM

Booth multiplier recoding table.

Booth Algorithm
 Best case – a long string of 1’s (skipping over 1s)
 Worst case – 0’s and 1’s are alternating
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Worst-case
multiplier
+1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1

1 1 0 0 0 1 0 1 1 0 1 1 1 1 0 0
Ordinary
multiplier
0 -1 0 0 + 1 - 1 +1 0 - 1 +1 0 0 0 -1 0 0

0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1
Good
multiplier
0 0 0 +1 0 0 0 0 -1 0 0 0 +1 0 0 -1
Bit-Pair Recoding of Multipliers
The pair (+1 -1) = ( 0 +1), means instead of adding -1
times M at shift position i to +1*M at position i+1, the
same result is obtain by adding +1*M at position i+1.
The pair (+1 0) = ( 0 +2),
The pair (-1 +1) = ( 0 -1),
Bit-Pair Recoding of Multipliers
Bit-pair recoding halves the maximum number of
summands (versions of the multiplicand).
Sign extension Implied 0 to right of LSB
1 1 1 0 1 0 0

0 0 1 +1 1 0

0 1 2

(a) Example of bit-pair recoding derived from Booth recoding

Bit-Pair Recoding of Multipliers
Multiplier bit-pair Multiplier bit on the right Multiplicand
i +1 i i 1 selected at position
i

0 0 0 0 X M
0 0 1 +1 X M
0 1 0 +1 X M
0 1 1 +2 X M
1 0 0 2 X M
1 0 1 1 X M
1 1 0 1 X M
1 1 1 0 X M

(b) Table of multiplicand selection decisions

Bit-Pair Recoding of Multipliers
0 1 1 0 1
0 - 1 +1 - 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 1 1 0 1 ( + 13) 0 0 0 0 0 0
 1 1 0 1 0 - 6  1 1 1 0 1 1 0 0 1 0  - 78 

0 1 1 0 1
0 -1 -2
1 1 1 1 1 0 0 1 1 0
1 1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 0

Figure 6.15. Multiplication requiring only n/2 summands.28

Carry-Save Addition of Summands
 CSA speeds up the addition process.

P7 P6 P5 P4 P3 P2 P1 29P0
 Carry-Save Addition of Summands(Cont.,)

P7 P6 P5 P4 P3 P2 P1 P0
Carry-Save Addition of
Summands(Cont.,)
Consider the addition of many summands, we can:
 Group the summands in threes and perform carry-save addition on
each of these groups in parallel to generate a set of S and C vectors in
one full-adder delay
 Group all of the S and C vectors into threes, and perform carry-save
addition on them, generating a further set of S and C vectors in one
more full-adder delay
 Continue with this process until there are only two vectors remaining
 They can be added in a RCA or CLA to produce the desired product
Carry-Save Addition of Summands
1 0 1 1 0 1 (45) M

X 1 1 1 1 1 1 (63) Q

1 0 1 1 0 1 A
1 0 1 1 0 1 B

1 0 1 1 0 1 C
1 0 1 1 0 1 D
1 0 1 1 0 1 E
1 0 1 1 0 1 F

1 0 1 1 0 0 0 1 0 0 1 1 (2,835) Product

Figure 6.17. A multiplication example used to illustrate carry-save addition as shown in Figure 6.18.
 1 0 1 1 0 1 M

x 1 1 1 1 1 1 Q

1 0 1 1 0 1 A

1 0 1 1 0 1 B

1 0 1 1 0 1 C

1 1 0 0 0 0 1 1 S
1
0 0 1 1 1 1 0 0 C
1

1 0 1 1 0 1 D
1 0 1 1 0 1 E
1 0 1 1 0 1 F

1 1 0 0 0 0 1 1 S
2
0 0 1 1 1 1 0 0 C
2

1 1 0 0 0 0 1 1 S1

0 0 1 1 1 1 0 0 C
1
1 1 0 0 0 0 1 1 S2
1 1 0 1 0 1 0 0 0 1 1 S
3
0 0 0 0 1 0 1 1 0 0 0 C3
0 0 1 1 1 1 0 0 C2
0 1 0 1 1 1 0 1 0 0 1 1 S4
+ 0 1 0 1 0 1 0 0 0 0 0 C
4
1 0 1 1 0 0 0 1 0 0 1 1 Product

Figure 6.18. The multiplication example from Figure 6.17 performed using
carry-save addition.
 If b is a binary vector, then we have seen that it can be interpreted as
an unsigned integer by:
V(b) = b31.231 + b30.230 + bn-3.229 + .... + b1.21 + b0.20

This vector has an implicit binary point to its immediate right:

b31b30b29....................b1b0. implicit binary point

Suppose if the binary vector is interpreted with the implicit binary point is
just left of the sign bit:
implicit binary point .b31b30b29....................b1b0

The value of b is then given by:

V(b) = b31.2-1 + b30.2-2 + b29.2-3 + .... + b1.2-31 + b0.2-32

The value of the unsigned binary fraction is:
V(b) = b31.2-1 + b30.2-2 + b29.2-3 + .... + b1.2-31 + b0.2-32

The range of the numbers represented in this format is:

0  V (b)  1  2 32  0.9999999998

In general for a n-bit binary fraction (a number with an assumed binary

point at the immediate left of the vector), then the range of values is:

0  V (b)  1  2  n
•Previous representations have a fixed point. Either the point is to the immediate
right or it is to the immediate left. This is called Fixed point representation.
•Fixed point representation suffers from a drawback that the representation can
only represent a finite range (and quite small) range of numbers.

A more convenient representation is the scientific representation, where

the numbers are represented in the form:

x  m1 .m 2 m3 m4  b e
Components of these numbers are:

Mantissa (m), implied base (b), and exponent (e)

A number such as the following is said to have 7 significant digits

x  0.m1 m2 m 3 m4 m 5 m6 m7  b e

Fractions in the range 0.0 to 0.9999999 need about 24 bits of precision

(in binary). For example the binary fraction with 24 1’s:
111111111111111111111111 = 0.9999999404

Not every real number between 0 and 0.9999999404 can be represented

by a 24-bit fractional number.
The smallest non-zero number that can be represented is:

000000000000000000000001 = 5.96046 x 10-8

Every other non-zero number is constructed in increments of this value.

•In a 32-bit number, suppose we allocate 24 bits to represent a fractional
mantissa.
•Assume that the mantissa is represented in sign and magnitude format,
and we have allocated one bit to represent the sign.
•We allocate 7 bits to represent the exponent, and assume that the
exponent is represented as a 2’s complement integer.
•There are no bits allocated to represent the base, we assume that the
base is implied for now, that is the base is 2.
•Since a 7-bit 2’s complement number can represent values in the range
-64 to 63, the range of numbers that can be represented is:

0.0000001 x 2-64 < = | x | <= 0.9999999 x 263

•In decimal representation this range is:

0.5421 x 10-20 < = | x | <= 9.2237 x 1018

 1 7 24

Sign Exponent Fractional mantissa

bit
•24-bit mantissa with an implied binary point to the immediate left
•7-bit exponent in 2’s complement form, and implied base is 2.
 Consider the number: x = 0.0004056781 x 1012

If the number is to be represented using only 7 significant mantissa digits,

the representation ignoring rounding is: x = 0.0004056 x 1012

If the number is shifted so that as many significant digits are brought into
7 available slots:
x = 0.4056781 x 109 = 0.0004056 x 1012

Exponent of x was decreased by 1 for every left shift of x.

A number which is brought into a form so that all of the available mantissa
digits are optimally used (this is different from all occupied which may
not hold), is called a normalized number.

Same methodology holds in the case of binary mantissas

0001101000(10110) x 28 = 1101000101(10) x 25
•A floating point number is in normalized form if the most significant
1 in the mantissa is in the most significant bit of the mantissa.
•All normalized floating point numbers in this system will be of the form:

0.1xxxxx.......xx

Range of numbers representable in this system, if every number must be

normalized is:
0.5 x 2-64 <= | x | < 1 x 263
 The procedure for normalizing a floating point number is:
Do (until MSB of mantissa = = 1)
Shift the mantissa left (or right)
Decrement (increment) the exponent by 1
end do

Applying the normalization procedure to: .000111001110....0010 x 2-62

gives: .111001110........ x 2-65

But we cannot represent an exponent of –65, in trying to normalize the

number we have underflowed our representation.
Applying the normalization procedure to: 1.00111000............x 263
gives: 0.100111..............x 264

This overflows the representation.

So far we have assumed an implied base of 2, that is our floating point
numbers are of the form:
x = m 2e

If we choose an implied base of 16, then:

x = m 16e

Then:
y = (m.16) .16e-1 (m.24) .16e-1 = m . 16e = x

•Thus, every four left shifts of a binary mantissa results in a decrease of 1

in a base 16 exponent.
•Normalization in this case means shifting the mantissa until there is a 1 in
the first four bits of the mantissa.
•Rather than representing an exponent in 2’s complement form, it turns out to be
more beneficial to represent the exponent in excess notation.
•If 7 bits are allocated to the exponent, exponents can be represented in the range
of -64 to +63, that is:
-64 <= e <= 63
Exponent can also be represented using the following coding called as excess-64:

E’ = Etrue + 64
In general, excess-p coding is represented as:
E’ = Etrue + p

True exponent of -64 is represented as 0

0 is represented as 64
63 is represented as 127

This enables efficient comparison of the relative sizes of two floating point numbers.
IEEE Floating Point notation is the standard representation in use. There are two
representations:
- Single precision.
- Double precision.
Both have an implied base of 2.
Single precision:
- 32 bits (23-bit mantissa, 8-bit exponent in excess-127 representation)
Double precision:
- 64 bits (52-bit mantissa, 11-bit exponent in excess-1023 representation)
Fractional mantissa, with an implied binary point at immediate left.

Sign Exponent Mantissa

1 8 or 11 23 or 52
•Floating point numbers have to be represented in a normalized form to
maximize the use of available mantissa digits.
•In a base-2 representation, this implies that the MSB of the mantissa is
always equal to 1.
•If every number is normalized, then the MSB of the mantissa is always 1.
We can do away without storing the MSB.
•IEEE notation assumes that all numbers are normalized so that the MSB
of the mantissa is a 1 and does not store this bit.
•So the real MSB of a number in the IEEE notation is either a 0 or a 1.
•The values of the numbers represented in the IEEE single precision
notation are of the form:
(+,-) 1.M x 2(E - 127)
•The hidden 1 forms the integer part of the mantissa.
•Note that excess-127 and excess-1023 (not excess-128 or excess-1024) are used
to represent the exponent.
In the IEEE representation, the exponent is in excess-127 (excess-1023)
notation.
The actual exponents represented are:

-126 <= E <= 127 and -1022 <= E <= 1023

not
-127 <= E <= 128 and -1023 <= E <= 1024

This is because the IEEE uses the exponents -127 and 128 (and -1023 and
1024), that is the actual values 0 and 255 to represent special conditions:
- Exact zero
- Infinity
Addition:
3.1415 x 108 + 1.19 x 106 = 3.1415 x 108 + 0.0119 x 108 = 3.1534 x 108
Multiplication:
3.1415 x 108 x 1.19 x 106 = (3.1415 x 1.19 ) x 10(8+6)

Division:
3.1415 x 108 / 1.19 x 106 = (3.1415 / 1.19 ) x 10(8-6)

Biased exponent problem:

If a true exponent e is represented in excess-p notation, that is as e+p.
Then consider what happens under multiplication:

a. 10(x + p) * b. 10(y + p) = (a.b). 10(x + p + y +p) = (a.b). 10(x +y + 2p)

Representing the result in excess-p notation implies that the exponent

should be x+y+p. Instead it is x+y+2p.
Biases should be handled in floating point arithmetic.
Floating point arithmetic: ADD/SUB
rule
Choose the number with the smaller exponent.
Shift its mantissa right until the exponents of both the
numbers are equal.
Add or subtract the mantissas.
Determine the sign of the result.
Normalize the result if necessary and truncate/round
to the number of mantissa bits.

Note: This does not consider the possibility of overflow/underflow.

Floating point arithmetic: MUL rule
Add the exponents.
Subtract the bias.
Multiply the mantissas and determine the sign of the
result.
Normalize the result (if necessary).
Truncate/round the mantissa of the result.
Floating point arithmetic: DIV rule
Subtract the exponents
Add the bias.
Divide the mantissas and determine the sign of the
result.
Normalize the result if necessary.
Truncate/round the mantissa of the result.

Note: Multiplication and division does not require alignment of the

mantissas the way addition and subtraction does.
While adding two floating point numbers with 24-bit mantissas, we shift
the mantissa of the number with the smaller exponent to the right until
the two exponents are equalized.
This implies that mantissa bits may be lost during the right shift (that is,
bits of precision may be shifted out of the mantissa being shifted).
To prevent this, floating point operations are implemented by keeping
guard bits, that is, extra bits of precision at the least significant end
of the mantissa.
The arithmetic on the mantissas is performed with these extra bits of
precision.
After an arithmetic operation, the guarded mantissas are:
- Normalized (if necessary)
- Converted back by a process called truncation/rounding to a 24-bit
mantissa.
Truncation/rounding
Straight chopping:
 The guard bits (excess bits of precision) are dropped.

Von Neumann rounding:

 If the guard bits are all 0, they are dropped.
 However, if any bit of the guard bit is a 1, then the LSB of the retained bit is
set to 1.
Rounding:
 If there is a 1 in the MSB of the guard bit then a 1 is added to the LSB of the
retained bits.
Rounding
Rounding is evidently the most accurate truncation
method.
However,
 Rounding requires an addition operation.
 Rounding may require a renormalization, if the addition operation de-

normalizes the truncated number.

0.111111100000 rounds to 0.111111 + 0.000001
=1.000000 which must be renormalized to 0.100000

IEEE uses the rounding method.