UNIT - 2

Arithmetic Unit
 Table of Contents

Addition and subtraction of signed numbers

 Design of fast adders
 Multiplication of positive numbers
 Signed operand multiplication,
 Fast multiplication- Bit pair recoding of Multipliers,
 Carry Save Addition of summands
 Integer division – Restoring Division and Non
Restoring Division
 Floating point numbers and operations
Addition/subtraction of signed numbers
xi yi Carry-in ci Sum s i Carry-out c i+1
At the ith stage:
0 0 0 0 0 Input:
0 0 1 1 0 ci is the carry-in
0 1 0 1 0
0 1 1 0 1 Output:
1 0 0 1 0 si is the sum
1 0 1 0 1
1 1 0 0 1 ci+1 carry-out to (i+1)st
1 1 1 1 1 state
si = xi yi ci + xi yi ci + xi yi ci + xi yi ci = x i  yi  ci
ci +1 = yi c i + x i ci + x i y i

Example:

X 7 0 1 1 1 Carry-out xi Carry-in
+ Y = +6 = +00 1 1 1 1 0 0 0 yi
ci+1 ci
Z 13 1 1 0 1 si

Legend for stage i

 Addition logic for a single stage
Sum Carry
yi
c
i
xi
xi
yi si c
c i +1
i
ci
x
xi yi i
yi

ci + 1 Full adder ci
(FA)

s
i

Full Adder (FA): Symbol for the complete circuit

for a single stage of addition.
 n-bit adder

•Cascade n full adder (FA) blocks to form a n-bit adder.

•Carries propagate or ripple through this cascade, n-bit ripple carry adder.

xn - 1
yn- 1 x1 y1 x0 y0

cn - 1
c1
cn FA FA FA c0

sn - 1
s1 s0
Most significant bit Least significant bit
(MSB) position (LSB) position

Carry-in c0 into the LSB position provides a convenient way to

perform subtraction.
ALU Inputs and Outputs
 Integer Representation

• Only have 0 & 1 to represent everything

• Positive numbers stored in binary
– e.g. 41=00101001
• No minus sign
• No period
• Sign-Magnitude
• One's Complement
• Two’s compliment
 Integer Representation (cont’d)

• Sign Magnitude: One's Complement Two's

Complement
000 = +0 000 = +0 000 = +0
001 = +1 001 = +1 001 = +1
010 = +2 010 = +2 010 = +2
011 = +3 011 = +3 011 = +3
100 = -0 100 = -3 100 = -4
101 = -1 101 = -2 101 = -3
110 = -2 110 = -1 110 = -2
111 = -3 111 = -0 111 = -1

• Issues: balance, number of zeros, ease of operations

• Which one is best? Why?
 Two's Complement Operations
• Negating a two's complement number: invert all bits and
add 1
– remember: “negate” and “invert” are quite different!

• Converting n bit numbers into numbers with more than n

bits:
– MIPS 16 bit immediate gets converted to 32 bits for arithmetic
– copy the most significant bit (the sign bit) into the other bits
0010 -> 0000 0010
1010 -> 1111 1010
– "sign extension" (lbu vs. lb)
Signed and unsigned additions

• Unsigned addition • Signed addition in

4-bit arithmetic
in 4-bit arithmetic ( carry) 11_
1011
( carry) 11_ + 0011
1110
1011 • -5 + 3 = -2

+ 0011
1110
• 11 + 3 = 14
(8 + 4 + 2)
Signed and unsigned additions

• Same rules apply even though bit strings

represent different values
• Sole difference is overflow handling
 Sign-Magnitude

• Left most bit is sign bit

• 0 means positive
• 1 means negative
• +18 = 00010010
• -18 = 10010010
• Problems
– Need to consider both sign and magnitude in
arithmetic
– Two representations of zero (+0 and -0)
 Range of Numbers

• 8 bit 2s compliment
– +127 = 01111111 = 27 -1
– -128 = 10000000 = -27
• 16 bit 2s compliment
– +32767 = 011111111 11111111 = 215 - 1
– -32768 = 100000000 00000000 = -215
 Conversion Between Lengths

• Positive number pack with leading zeros

• +18 = 00010010
• +18 = 00000000 00010010
• Negative numbers pack with leading ones
• -18 = 10010010
• -18 = 11111111 10010010
• i.e. pack with MSB (sign bit)
 Addition and Subtraction

• Normal binary addition

• Monitor sign bit for overflow

• Take twos compliment of substahend and add

to minuend
– i.e. a - b = a + (-b)

• So we only need addition and complement

circuits
Hardware for Addition and
Subtraction
 Adders and Simple ALUs

Addition is the most important arithmetic operation in computers:

– Even the simplest computers must have an adder
– An adder, plus a little extra logic, forms a simple ALU

• Simple Adders

• Carry Lookahead Adder

• Counting and Incrementing

• Design of Fast Adders

• Logic and Shift Operations

• Multifunction ALUs
Full adder
si Assum
= xi e3 y
- i/i  ci gate for S and SOP
p XOR i
T form
D = 1 (or 2for
); C i+ 1

ci+1 = xi . yi + ci . (xi + yi) T = 2 ; D

Ripple-Carry Adder

c4

2 N;
O  Cn  Cn1; TD/C = 2 N-1 ;

TD/S = 2 N+2
O  xn1 yn1 S n1  xn1 yn1Sn1 TD/O =
 Building a 32 bit ALU CarryIn Operation

a0 CarryIn
Operation ALU0
Result0
b0
CarryIn CarryOut

19
a a1 CarryIn
0 ALU1
Result1
b1
CarryOut

1
Result
a2 CarryIn
Result2
ALU2
b2
2 CarryOut
b

CarryOut
a31 CarryIn
Result31
ALU31
b31
 CarryIn

Carry-lookahead adder (3) a0

b0
CarryIn
Result0--3
a1
b1 ALU0
a2 pi
b2 P0
G0 gi
a3
b3 Carry-lookahead unit
C1
• Use principle to build bigger ci + 1

adders a4
b4
CarryIn
Result4--7
a5
• Can’t build a 16 bit adder this b5
a6
ALU1
pi + 1
P1
b6 G1 gi + 1
way... (too big) a7
b7
C2
• Could use ripple carry of 4-bit ci + 2

CLA adders a8
b8
CarryIn
Result8--11
a9
• Better: use the CLA principle b9
a10
ALU2
P2 pi + 2
b10 G2 gi + 2
again! a11
b11
C3
ci + 3

a12 CarryIn
b12 Result12--15
a13
b13 ALU3
a14 P3 pi + 3
b14 G3 gi + 3
a15 C4
b15 ci + 4
20
CarryOut
 Detecting Overflow
• No overflow when adding a positive and a negative number

• No overflow when signs are the same for subtraction

• Overflow occurs when the value affects the sign:

– overflow when adding two positives yields a negative
– or, adding two negatives gives a positive
– or, subtract a negative from a positive and get a negative
– or, subtract a positive from a negative and get a positive

• Consider the operations A + B, and A – B

– Can overflow occur if B is 0 ?
– Can overflow occur if A is 0 ?
 16-bit Group Carry Lookahead Adder
• A16-bit GCLA is composed of four 4-bit CLAs, with
additional logic that generates the carries between the
four-bit groups.
GG0 = G3 + P3G2 + P3P2G1 + P3P2P1G0
GP0 = P3P2P1P0
c4 = GG0 + GP0c0
c8 = GG1 + GP1c4 = GG1 + GP1GG0 + GP1GP0c0
c12 = GG2 + GP2c8 = GG2 + GP2GG1 + GP2GP1GG0 +
GP2GP1GP0c0
c16 = GG3 + GP3c12 = GG3 + GP3GG2 + GP3GP2GG1 +
GP3GP2GP1GG0 + GP3GP2GP1GP0c0
 16-Bit Group Carry Lookahead Adder

• Each CLA has

a longest path
of 5 gate
delays.

• In the GCLL section, GG and GP signals are generated

in 3 gate delays; carry signals are generated in 2 more
gate delays, resulting in 5 gate delays to generate the
carry out of each GCLA group and 10 gates delays on
the worst case path (which is s15 – not c16).
 Multiplication

• Complex
• Work out partial product for each digit
• Take care with place value (column)
• Add partial products
 Multiplication Example

• 1011 Multiplicand (11 dec)

• x 1101 Multiplier (13 dec)
• 1011 Partial products
• 0000 Note: if multiplier bit is 1 copy
• 1011 multiplicand (place value)
• 1011 otherwise zero
• 10001111 Product (143 dec)
• Note: need double length result
Unsigned Binary Multiplication
Execution of Example
Flowchart for Unsigned Binary
Multiplication
Multiplying Negative Numbers

• This does not work!

• Solution 1
– Convert to positive if required
– Multiply as above
– If signs were different, negate answer
• Solution 2
– Booth’s algorithm
Booth’s Algorithm
Example of Booth’s Algorithm
 FAST MULTIPLICATION
*BOOTH RECODING OF MULTIPLERS
* BIT PAIR RECODING OF MULTIPLIERS
CARRY SAVE ADDITION OF SUMMANDS
 The BOOTH RECODED MULTIPLIER
• Booth multiplication reduces the number of additions for
intermediate results, but can sometimes make it worse as
we will see.
• Positive and negative numbers treated alike.
 A Worst Case Booth Example
• A worst case situation in which the simple Booth
algorithm requires twice as many additions as serial
multiplication.
Bit-Pair Recoding (Modified Booth Algorithm)
Coding of Bit Pairs
 Carry Save Addition of
Summands

• CSA can be used to speed up addition of the

several summands required in multiplication
Ripple Carry Array
Carry – Save Array
 Fast Multiplication

• Bit pair recoding reduces summands by a

factor of 2
• Summands are reduced by carry – save
addition
• Final product can be generated by using carry
lookahead adder
 Division

• More complex than multiplication

• Negative numbers are really bad!
• Based on long division
Division of Unsigned Binary
Integers

00001101 Quotient

Divisor 1011 10010011 Dividend

1011
001110
Partial
1011
Remainders
001111
1011
Remainder
100
Flowchart for Unsigned Binary
Division
 Real Numbers

• Numbers with fractions

• Could be done in pure binary
– 1001.1010 = 23 + 20 +2-1 + 2-3 =9.625
• Where is the binary point?
• Fixed?
– Very limited
• Moving?
– How do you show where it is?
 Floating Point

• +/- .significand x 2exponent

• Misnomer
• Point is actually fixed between sign bit and body of mantissa
• Exponent indicates place value (point position)

Misnomer:เรี ยกชื่อผิด, ใช้ ชื่อผิด

Floating Point Examples
 Signs for Floating Point

• Mantissa is stored in 2s compliment

• Exponent is in excess or biased notation
– e.g. Excess (bias) 128 means
– 8 bit exponent field
– Pure value range 0-255
– Subtract 128 to get correct value
– Range -128 to +127
 Normalization

• FP numbers are usually normalized

• i.e. exponent is adjusted so that leading bit
(MSB) of mantissa is 1
• Since it is always 1 there is no need to store it
• (c.f. Scientific notation where numbers are
normalized to give a single digit before the
decimal point
• e.g. 3.123 x 103)
 FP Ranges

• For a 32 bit number

– 8 bit exponent
– +/- 2256  1.5 x 1077
• Accuracy
– The effect of changing lsb of mantissa
– 23 bit mantissa 2-23  1.2 x 10-7
– About 6 decimal places
Expressible Numbers
Density of Floating Point
Numbers
 IEEE 754

• Standard for floating point storage

• 32 and 64 bit standards
• 8 and 11 bit exponent respectively
• Extended formats (both mantissa and
exponent) for intermediate results
IEEE 754 Formats
 FP Arithmetic +/-

• Check for zeros

• Align significands (adjusting exponents)
• Add or subtract significands
• Normalize result
FP Addition & Subtraction
Flowchart
 FP Arithmetic x/

• Check for zero

• Add/subtract exponents
• Multiply/divide significands (watch sign)
• Normalize
• Round
• All intermediate results should be in double
length storage
Floating Point Multiplication
Floating Point Division
 Floating-point Computations

• Representation: (fraction, exponent) Has three fields:

sign, significant digits and exponent
eg.111101.100110 1.11101100110*25

• Value representation = +/- M*2 E’-127

In case of a 32 bit number 1 bit represents sign
8 bits represents exponent E’=E +127(bias) [ excess 127
format]
23 bits represents Mantissa
 Floating-point Computations

• Arithmetic operations
.5372400 x 102 .5372400 x 102 .56780 x 105
+ .1580000 x 10-1 + .0001580 x 102 + .56430 x 105
.5373980 x 102 .00350 x 105

.35000 x 103

.5372400 x 102
x .1580000 x 10-1

Addition
 Floating-point Computations
• Biased Exponent
– Bias: an excess number added to the exponent so that all exponents
become positive
– Advantages
• Only positive exponents
• Simpler to compare the relative magnitude
 Floating-point Computations

• Standard Operand Format of floating-point numbers

– Single-precision data type: 32bits
• ADDFS
– Double-precision data type: 64bits
• ADDFL

IEEE Floating-Point Operand Format

 Floating-point Computations

• Significand
– A leading bit to the left of the implied binary point, together with the
fraction in the field

f field Significand Decimal Equivalent

100…0 1.100…0 1.50
010…0 1.010…0 1.25
000…0 1.000…0 1.00

~ ~
Minimum number 01000..000 Maximum number
Thank You.