UNIT – 3 Instruction Set Characteristics

• The words of a machine language are known as

instructions, and its syntax is known as an instruction
set.
• Instruction set is the boundary where the computer
designer arid the computer
programmer see the same computer from different
viewpoints.
• From the designer's point of view, the computer
instruction set provides a functional description of a
processor, that is:
(i) A detailed list of the instructions that a processor is
capable of processing.
(ii) A description of the types/ locations/ access methods for
operands.
 Instruction Set Characteristics
• The common goal of computer designers is to build
the hardware for implementing the machine's
instructions for CPU.
• From the programmer's point of view, the user must
understand machine or assembly language for low-
level programming.
• Moreover, the user must be aware of the register set,
instruction types and the function that each instruction
performs.
• Instruction set is the collection of machine language
instructions that a particular processor understands
and executes.
• In other words, a set of assembly language mnemonics
represents the machine code of a particular computer.
 Instruction Set Characteristics
• Instructions can take different formats. The instruction
format involves:
- the instruction length ;
-the type;
-length and position of operation codes in an instruction;
-and the number and length of operand addresses etc.
 Instruction Set Characteristics
Elements of an Instruction
• As the purpose of instruction is to communicate to
CPU what to do, it requires a minimum set of
communication as:
-What operation to perform?
-On what operands?
• Thus, each instruction consists of several fields. The
most common fields found in instruction formats are:
-Opcode: (What operation to perform?)
An operation code field termed as opcode that specifies
the operation to be performed.
 Instruction Set Characteristics
Elements of an Instruction
-Operands: (Where are the operands?)
• An address field of operand on which data processing
is to be performed.
• An operand can reside in the memory or a processor
register or can be incorporated within the operand field
of instruction as an immediate constant.
• Therefore a mode field is needed that specifies the way
the operand or its address is to be determined.

• A sample instruction format is given in figure 1.

6 bits 2 bits 24 bits

Opcode Address Mode Operand or address of operand

Instruction Length of 32 bits

 Instruction Set Design Considerations
INSTRUCTION SET DESIGN
CONSIDERATIONS
• Some of the basic considerations for instruction set
design include selection of:
- A set of data types (e.g. integers, long integers,
doubles, character strings etc.).
- A set of operations on those data types. '
- A set of instruction formats. Includes issues like
number of addresses, instruction length etc.
- A set of techniques for addressing data in memory or in
registers.
- The number of registers which can be referenced by an
instruction and how they are used.
 Instruction Set Design Considerations
OPERAND DATA TYPES

Logical Data
Addresses Numbers Characters 0 or 1 value
only

Floating point Fixed Point Binary Coded

Single or Double Signed or Decimal
Precision Unsigned
 Instruction Set Design Considerations
OPERAND DATA TYPES
• Addresses
- Operands residing in memory are specified by their
memory address and operands residing in registers are
specified by a register address. Addresses provided in
the instruction are operand references.
• Numbers
- All machine languages include numeric data types.
Numeric data usually use one of three representations:
Floating-point numbers-single precision (1 sign bit, 8
exponent bits, 23 mantissa bits) and double precision
(1 sign bit, 11 exponent bits, 52 mantissa bits).
- Fixed point numbers(signed or unsigned)
 Instruction Set Design Considerations
OPERAND DATA TYPES
• Characters
- A common form of data is text or character strings.
Characters are represented in numeric form, mostly in
ASCII (American Standard Code for Information
Exchange). Another Code used to encode characters is
the Extended Binary Coded Decimal Interchange Code
(EBCDIC).
• Logical Data
- Each word or byte is treated as a single unit of data.
When an n-bit data unit is considered as consisting of n
1 -bit items of data with each item having the value 0 or
1, then they are viewed as logical data.
 Instruction Set Design Considerations
TYPES OF INSTRUCTIONS

Data Transfer Data Processing Program Miscellaneous

Instructions Instructions Control Privileged
Instructions
 Instruction Set Design Considerations
• DATA TRANSFER INSTRUCTIONS
- These instructions transfer data from one location in
the computer to another location without changing the
data content.
- The most common transfers are between:
• processor registers and memory,
• processor registers and I/0, and
• processor registers themselves.

-These instructions need:

• the location of source and destination operands,
• and the mode of addressing for each operand.
 Instruction Set Design Considerations
Operation Name Mnemonics Description

Load LD Load the contents from memory to register

Store ST Store the information from register to memory location

Move MOV Data transfer from one register to another or between

CPU registers and memory
Exchange XCH Swaps information between two registers or a register
and a memory word
Clear CLEAR Causes the specified operand to be replaced by 0’s

Set SET Causes the specified operand to be replaced by 1’s

Push PUSH Transfers data from a register to top of memory stack

Pop POP Transfers data from a top of memory stack to register

DATA TRANSFER INSTRUCTIONS

 Instruction Set Design Considerations
• DATA PROCESSING INSTRUCTIONS
-These instructions perform arithmetic and logical
operations on data.
-Data manipulation Instructions can be divided into three
basic types:
i) Arithmetic
-The four basic operations are ADD, SUB, MUL and DIV.
-An arithmetic instruction may operate on fixed-point
data, binary or decimal data etc.
-The other possible operations include a variety of
single-operand instructions, for example
ABSOLUTE, NEGATE, INCREMENT, DECREMENT.
-The execution of arithmetic instructions requires
bringing in the operands in the operational registers so
 Instruction Set Design Considerations
ii) Logical
- AND. OR, NOT, XOR operate on binary data stored in
registers.
- For example, if two registers contain the data:
R1=10110111 R2=11110000
Then R1 AND R2 = 10 1 1 0000.
Then R1 XOR R2 = 01000111
iii) Shift
-Shift operation is used for transfer of bits either to the
left or to the right. It can be used to realize simple
arithmetic operation or data
communication/recognition etc.
-Shift operation is of three types:
 Instruction Set Design Considerations
a) Logical shifts LOGICAL SHIFT LEFT and LOGICAL
SHIFT RIGHT insert zeros to the end bit position and the
other bits of a word are shifted left or right respectively.
-The end bit position is the leftmost bit for shift right and
the rightmost bit position for the shift left. The bit shifted
out is lost.

Logical Shift Left

0

Logical Shift Right

 Instruction Set Design Considerations
b) Arithmetic shifts ARITHMETIC SHIFT LEFT and
ARITHMETIC SHIFT RIGHT are the same as LOGICAL
SHIFT LEFT and LOGICAL SHIFT RIGHT except that
the sign bit it remains unchanged. On an arithmetic shift
right, the sign bit is replicated into the bit position to its
right.
-On an arithmetic shift left, a logical shift left is
performed on all bits but the sign bit, which is retained.

c) Circular shifts ROTATE LEFT and ROTATE RIGHT.

Bits shifted out at one end of the word are not lost as in
a logical shift but are circulated back into the other end.
 Instruction Set Design Considerations
• PROGRAM CONTROL INSTRUCTIONS
-These instructions specify conditions for altering the
sequence of program execution or in other words the
content of PC (program counter) register.
-PC points to memory location that holds the next
instruction to be executed.
-The change in value of-PC as a result of execution of
control instruction like BRANCH or JUMP causes a
break in the sequential execution of instructions.
-The most common control instructions are:
 Instruction Set Design Considerations
• BRANCH and JUMP may be conditional or
unconditional.
MBR  0 ; Assign 0 to MBR register
X  2001 ; Assume X to be an address location 2001
READ X ; Read a value from memory location 2001 into
AC
BRZ 1007 ; Branch to location 1007 if AC is zero
(Conditional branch on zero)
ADD MBR ; Add the content of MBR to AC and store
result to AC
TRAS MBR ; Transfer the contents of AC to MBR
INC X ; Increment X to point to next location
JUMP 1001 ; Loop back for further processing.
(a) A program on hypothetical machine
Instruction Set Design Considerations

0FFF MBR  0
1000 X  2001
1001 READ X
1002 BRZ 1007
1003 ADD MBR
1004 TRANS MBR
1005 INC X
1006 JUMP 1001
1007 .
.
.
2001 10
2002 20
2003 30
2004 0

The memory of the hypothetical machine

BRANCH and JUMP instructions

 Instruction Set Design Considerations
• 1001(with location x=2001 which is value 10) 
1002  1003  1004 1005(X is increment to 2002) 
1006 (1st Cycle)

• 1001(with location X=2001 which is value 20) 

1002  1003  1004 1005(X is increment to 2003) 
1006 (2nd Cycle)

• 1001(with location X=2001 which is value 30) 

1002  1003  1004 1005(X is increment to 2004) 
1006 (3rd Cycle)

• 1001(with X=2004 which is value 0)  1002(AC

contains zero so take a branch to 1007)  1006 (4th
Cycle) 1007…… MBR contains the added value
 Instruction Set Design Considerations
• The SKIP instruction is a zero-address
instruction and skips the next instruction to be
executed in sequence. In other words, it
increments the value of PC by one instruction
length. The SKIP can also be conditional. For
example, the instruction ISZ skips the next
instruction only if the result of the most recent
operation is zero.
• CALL and RETN are used for CALLing
subprograms and RETurning from them.
Assume that a memory stack has been built
such that stack pointer points to a non-empty
location stack and expand towards zero
Instruction Set Design Considerations
 Instruction Set Design Considerations
• Miscellaneous and Privileged Instructions:
These instructions do not fit in any of the above
categories. 110 instructions: start I/O, stop I/O,
and test I/O.
-Typically, I/O destination is specified as an
address. Interrupts and state-swapping
operations: There are two kinds of exceptions,
interrupts that are generated by hardware and
traps, . which are generated by programs.
-Upon receiving interrupts, the state of current
processes will be saved so that they can be
restarted after the interrupt has been taken care
of.
 THE CONTROL UNIT
• The two basic components of a CPU are the
control unit and the arithmetic and logic unit. The
control unit of the CPU selects and interprets
program instructions and then sees that they are
executed. The basic responsibilities of the
control unit are to control :
a) Data exchange of CPU with the memory or I/O
modules.
b) Internal operation in the CPU such as :
- Moving data b/w registers(register transfer
operations)
- Making ALU to perform a particular operation on
the data.
- Regulating other internal operations.
 Functional Requirements of the Control Unit
• Let us first try to define the functions which a
control unit must perform in order to get things to
happen. But in order to define the functions of a
control unit, one must know what resources and
means it has at its disposal. A control unit must
know about the:
(a) Basic components of the CPU
(b) Micro-operation this CPU performs.
• The CPU of a computer consists of the following
basic functional components:
-The Arithmetic Logic Unit (ALU), which performs
the basic arithmetic and logical operations.
-Registers which are used for information storage
within the CPU.
 Functional Requirements of the Control Unit
- Internal Data Paths: These paths are useful for moving
the data between two registers or between a register and
ALU.
-External Data Paths: The roles of these data paths are
normally to link the CPU registers with the memory or I/O
interfaces. This role is normally fulfilled by the system bus.
-The Control Unit: This causes all the operations to
happen in the CPU.
• The micro-operations performed by the CPU can be
classified as:
-Micro-operations for data transfer from register-register,
register-memory, I/0-register etc.
-Micro- operations for performing arithmetic, logic and shift
operations. These micro-operations involve use of
registers for input and output.
 Functional Requirements of the Control Unit
• The micro-operations performed by the CPU can be
classified as:
-Micro-operations for data transfer from register-register,
register-memory, I/0- register etc.
-Micro- operations for performing arithmetic, logic and
shift operations. These micro-operations involve use of
registers for input and output.
• The basic responsibility of the control unit lies in the
fact that the control unit must be able to guide the
various components of CPU to perform a specific
sequence of micro-operations to achieve the execution
of an instruction.
 Functional Requirements of the Control Unit
• Thus the control unit must perform two basic functions:
-Cause the execution of a micro-operation.
-Enable the CPU to execute a proper sequence of
micro-operations, which is determined by the instruction
to be executed.
• But how are these two tasks achieved? The control unit
generates control signals, which in turn are responsible
for achieving the above two tasks. But, how are these
control signals generated?
Structure of Control Unit
A control unit has a set of input values on the basis of
which it produces an output control signal, which in turn
performs micro-operations. These output signals control
the execution of a program.
 Structure of the Control Unit
• A general model of control unit is shown in below
figure.
 Structure of the Control Unit
• The inputs to the control unit are:
-The Master Clock Signal: This signal causes micro-
operations to be performed in a square. In a single clock
cycle either a single or a set of simultaneous
microoperations can be performed. The time taken in
performing a single microoperation is also termed as
processor cycle time or the clock cycle time in some
machines.
-The Instruction Register: It contains the operation
code (opcode) and addressing mode bits of the
instruction. It helps in determining the various cycles to
be performed and hence determines the related micro-
operations, which are needed to be performed.
 Structure of the Control Unit
-Flags: Flags are used by the control unit for
determining the status of the CPU & the outcomes of a
previous ALU operation. For example, a zero flag if set
conveys to control unit that for instruction ISZ (skip the
next instruction if zero flag is set) the next instruction is
to be skipped. For such a case control unit cause
increment of PC by program instruction length, thus
skipping next instruction.
-Control Signals from Control Bus: Some of the
control signals are provided to the control unit through
the control bus. These signals are issued from outside
the CPU. Some of these signals are interrupt signals
and acknowledgement signals.
 Structure of the Control Unit
• On the basis of the input signals the control unit
activates certain output control signals, which in turn
are responsible for the execution of an instruction.
These output ) control signals are:
-Control signals, which are required within the CPU:
These control signals cause two types of micro-
operations, viz, for data transfer from one register to
another; and for performing an arithmetic, logic and shift
operation using ALU.
-Control signals to control bus: These control signals
transfer data from or to CPU register to or from memory
or I/O interface. These control signals are issued on the
control bus to activate a data path on the data / address
bus etc.
 Structure of the Control Unit
• A program execution consists of a sequence of
instruction cycles. Each instruction cycle is made up of
a number of sub cycles. One such simple subdivision
includes fetch, indirect, execute, and interrupt cycles,
with only fetch and execute cycles always occurring.
Each sub cycle involves one or more micro-operations.
• Let us revisit the micro-operations to discuss how the
events of any instruction cycle can be described as a
sequence of such micro-operations.
-Fetch Cycle The beginning of each instruction cycle is
the fetch cycle, and causes an instruction to be fetched
from memory.
The fetch cycle consists of four micro-operations that are
executed in three timing steps.
 Structure of the Control Unit
• The fetch cycle can be written as:
T1: MAR PC
T2 : MBR [MAR]
PC  PC+ 1
T3 : IR  MBR
where I is the instruction length. We assume that a
clock is available for timing purposes and that it emits
regularly spaced clock pulses. Each clock pulse defines
a time unit. Thus, all the units are of equal duration.
Each micro-operation can be performed within the time
of a single time unit. The notation (TI, T2, T3) represents
successive time units.
 Structure of the Control Unit
• In the first time unit the content of PC is moved to
MAR.
• In the second time unit the contents of memory
location specified by MAR is moved to MBR and the
contents of the PC is incremented by 1.
• In the third time unit tne content of MBR is moved lo IR.
 Structure of the Control Unit
• The Indirect Cycle
-Once an instruction is fetched, the next step is to fetch
the operands. Considering the example, the instruction
may have direct and indirect addressing modes.
-An indirect address is handled using indirect cycle.
-The following microoperations are required in the
indirect cycle:
TI : MAR  IR (address)
T2 : MBR  [MAR]
T3 : IR (address)  MBR (address)
-The MAR is loaded with the address field of IR register.
Then the memory is read to fetch the address of
operand, which is transferred to the address field of IR
through MBR as data is received in MBR during the read
operation.
 Structure of the Control Unit
• The Execute Cycle
-An add instruction that adds the contents of memory
location X to Register R1 with R1 storing the result:
ADD R1, X
-The sequence of micro-operations may be:
TI : MAR  IR (address)
T2: MBR  [MAR]
T3: R1  R1 + MBR
-At the beginning of the execute cycle IR contains the
ADD instruction and its direct operand address (memory
location X).
-At time TI, the address portion of the IR is transferred to
the MAR. At T2 the referenced memory location is read
into MBR. Finally, at T3 the contents of R1 and MBR are
added by the ALU.
 Structure of the Control Unit
• The Interrupt Cycle
-On completion of the execute cycle the current
instruction execution gets completed.
-At this point a test is made to determine whether any
enabled interrupts have occurred. If so, the interrupt
cycle is performed.
-This cycle does not execute an interrupt but causes
start of execution of Interrupt Service Program (ISR).
-The nature of this cycle varies greatly from one
machine to another.
-A typical sequence of micro-operations of the interrupt
cycle are:
 Structure of the Control Unit
TI: MBR PC
T2 : MAR  Save-Address
PC  ISR- Address
T3 : [MAR]  MBR
-At time TI, the contents of the PC are transferred to the
MBR, so that they can be saved for return from the
interrupt.
-At time T2 the MAR is loaded with the address at which
the contents of the PC are to be saved, and PC is
loaded with the address of the start of the interrupt-
servicing routine.
-At time T3 MBR, which contains the old value of the PC,
is stored in the memory. The processor is now ready to
begin the next instruction cycle