Scribd
Upload
1K views19 pages

Memory Reference Instruction

Memory reference instructions (MRIs) reference memory locations to perform operations. The seven types are AND, ADD, LDA, STA, BUN, BSA, and ISZ. AND performs a logical AND operation between memory and the accumulator. ADD adds memory to the accumulator. LDA loads memory to the accumulator. STA stores the accumulator in memory. BUN unconditionally branches to a memory location. BSA branches and saves the return address in memory. ISZ increments memory and skips if the result is zero.

Uploaded by

Deepak Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
1K views19 pages

Memory Reference Instruction

Memory reference instructions (MRIs) reference memory locations to perform operations. The seven types are AND, ADD, LDA, STA, BUN, BSA, and ISZ. AND performs a logical AND operation between memory and the accumulator. ADD adds memory to the accumulator. LDA loads memory to the accumulator. STA stores the accumulator in memory. BUN unconditionally branches to a memory location. BSA branches and saves the return address in memory. ISZ increments memory and skips if the result is zero.

Uploaded by

Deepak Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 19

Memory Reference Instruction

MRI Definition:
Memory reference instructions are those commands or instructions which are
In the custom to generate a reference to the memory. These instructions are
known as Memory Reference Instruction
TYPES OF MRI :
There are seven memory reference instruction which are as follows :
1. AND
2. ADD
3. LDA
4. STA
5. BUN
6. BSA
7. ISZ
Memory-Reference Instructions
Symbol Operation OPCODE Description Symbolic description
Decoder (Hexadecimal)

I=0 I=1
AND D0 0xxx 8xxx AND memory word to AC AC <- AC ^ M[AR]

ADD D1 1xxx 9xxx Add memory word to AC AC <- AC + M[AR], E <- Cout

LDA D2 2xxx Axxx Load memory word to AC AC <- M[AR]

STA D3 3xxx Bxxx Store content of AC in memory M[AR] <- AC

BUN D4 4xxx Cxxx Branch Unconditionally PC <- AR

BSA D5 5xxx Dxxx Branch and save return address M[AR] <- PC, PC <- AR +1

ISZ D6 6xxx Exxx Increment and skip if Zero M[AR] <- M[AR] + 1,
If M[AR] + 1 = 0 then PC <- PC+1
AND to AC
• This is an instruction that performs the AND logic Operation on pairs of bits in
AC and the memory word specified by the effective address.
• The result of the operation is transferred to AC.
• The microoperations that execute this instruction are:
D0T4 : DR <- M[AR]
D0T5 : AC <- AC ^ DR, SC <- 0
Timing Control of AND:
• The two timing signal are T4,T5.
• T4 transfer the operand from memory in DR.
• T5 transfer to AC result AND logic operation.
• T0 is to start a new instruction cycle.
ADD to AC:
• This Instruction adds the content of the memory word specified by the
effective address to the value of AC.
• The sum is transferred into AC and the output carry C out is transferred to
the E (extended accumulator ) flip-flop.
• The microoperations needed to execute this instruction are

D1T4 : DR <- M[AR]


D1T5 : AC <- AC + DR, E <- C out , SC <- 0
Timing Control of ADD
• Two timing signals t4 and t5. decoder d1 instead do used in AND instruction
• Instruction fetched from memory and decoder.
• Output determine the sequence of microoperation execution of a MRI.
LDA: Load to AC
• This instruction transfers the memory word specified by the effective
address to AC.
• It has no direct path from the but into AC.
• The adder and logic circuit receive information from DR. transfer to AC.
• Read from memory and transfer to the adder and logic circuit.
• The microoperations needed to execute this instruction are:

D0T4 : DR <- M[AR]


D0T5 : AC <- AC ^ DR, SC <- 0
STA: Store AC
• This instruction stores the content of AC into the memory word specified by the
effective address.
• Output of AC is applied to the bus
• And data input of memory is connected to the bus,
• We can execute this instruction with one microoperation:

D3T4 : M[AR] <- AC , SC <- 0


BUN: Branch Unconditionally
• This instruction transfers the program to the instruction specified by the effective
address.
• It allows Programmer to specify and instruction out of sequence.
• Pc holds the address of the instruction read from memory in the next instruction
cycle.
• The effective Address from AR is Transferred through the common bus to PC.
• Microinstruction:
• D4T4 : PC <- AR, SC <- 0
BSA: Branch and Save Return Address

• This Instruction is useful for branching to a portion of the program called a


subroutine or procedure.
• The BSA instruction stores the address of the next instruction in sequence
(which is available in PC ) into a memory location specified by the effective
address.
• The effective address plus one is then transferred to PC to serve as the
address of the first instruction in the subroutine.
BSA: Branch and Save Return Address
• Address of the first instruction in the subroutine.
• M[AR] <- PC, PC <- AR + 1

• Next Instruction is called return address.


• M[135] <- 21, PC <- 135 +1 = 136.

• End of the subroutine performs the function refer is called subroutine


return.
• D5T4 : M[AR] <- PC, AR <- AR+1
• D5T5 : PC <- AR, SC <- 0

• Enable the INR input of AR.


ISZ: Increment and skip if Zero
• This instruction increments the word specified by the effective address, and if
the incremented value is equal to 0, Pc is incremented by 1.
• First it write the word into DR which is read from memory, then DR is
Incremented, then store the word back into memory
• Microoperation
• D6T4 : DR <- M[AR]
• D6T5 : DR <- DR + 1
• D6T6 : M[AR] <- DR, if ( DR = 0 ) then ( PC <- PC + 1 ), SC <- 0
Control Flow Chart:
• Show the execution of the microoperation in seven memory reference
instruction.
• It is Performed to the timing signals for T4, T5 or t6 the timing signals
are operation code value.
• SC is the sequence counter and SC is Cleared to 0. is include to an last
timing signal.
• The increment and skip is zero(ISZ). To there are include three bit
counter
References:
1. https://www.tutorialspoint.com/what-are-memory-reference-instructions
2. https://www.slideshare.net/DeepikaT13/memory-reference-instruction-117530297
3. Computer System Architecture (Book) By M. Morris Mano

You might also like