DFT Q&A

By
Sharmipriya
1.what is Design for Testability (DFT)?
■ DFT is a technique that makes test generation and test application easier and cost effective.
■ DFT techniques help in making the internal flip-flop easily controllability (you can initialize
them into any value you want )and observability (means we can read ou values whenever we want
).
■ It is design approach aimed at making digital systems more easily testable.
■ A product which is difficult to test will cost more to test and will be a difficult target for reduction
of its associated testing cost.
■ The best way to ensure that a product is testable is to consider design for testability from the very
beginning during the design phase of the product life cycle.
■ It makes the circuit more controllable and observable by embedding test constructs into the
design.
2.Advantages of DFT?

■ Test generation is easy.

■ High quality testing is possible.
■ Reduces time to market.
■ Reduces test time.
3.Difference between structural testing and functional testing?

Functional testing Structural Testing

Without fault models. With fault models.

Manually generated design verification test patterns. Automatic test pattern generation (ATPG).

Slow and labor intensive. Efficient and automated.

Fault coverage not known Fault Coverage is a quantified metric.

More Test Patterns Less Test Patterns

Can be applied at the operating speed. Difficult to be applied at the speed the design is expected to work.
4.what is scan insertion ? How it works for DFT ?

■ To enable a scan test for a chip design, additional test logic must be inserted; this is
called “scan insertion”. Scan insertion consists of two steps:
■ 1. Replace plain memory cells like flipflops or latches by scan cells.
■ 2. Connect these together forming one or more chains.
■ Scan cells can be operated in two modes, the functional/mission mode used during
normal operation and the scan mode that allows shifting through the scan chains.
5.which tool you have used for scan insertion, ATPG, simulation and MBIST insertion ?

■ Scan insertion: Tessent – TestKompress

■ ATPG: Tessent – FastScan Modelsim
■ Simulation :Modelsim
■ MBIST insertion: Tessent – MBIST
■  
6.what are scan drc violations you faced? How you fixed ?
■ Violations that prevent scan insertion
■ •Uncontrollable or undefined clocks
■Fix : 1. Define the clocks using add_clocks <off state> <clock name>.
■ 2. MUX the clock input ,with test_mode signal selecting either test clock or the clock
generated from the internal circuitry(can be fixed using autofix )
■ •Uncontrollable asynchronous signals
■Asynchronous signals must be controlled to inactive signals.
■ Fix : 1. Define asynchronous signal’s state with add_clocks <inactive state> < Asynchronous
signal>
■ 2. MUX the asynchronous input, with test_mode signal selecting either global asynchronous
signal or internally generated signal (can be fixed using autofix)
■ Violations that prevent data capture

■ Clock used as data

■ When a clock signal drives the data pin of a cell, ATPG tools cannot determine the captured
value. Fix : Modify the logic leading to the
datapaths to eliminate dependency on the clock
■ Black box feeds into clock or asynchronous inputs.

■Violation :

■ Fix : It’s a special case of uncontrollable clocks and asynchronous signals. So it can be fixed
with the help of previously mentioned fixes. Since black box output will be always unknown,
select line of the MUX can be test_mode
■ Violations that reduce the coverage

■ Combinational feedback loops

■ A loop that oscillates causes severe problems for ATPG and for fault simulation
■ Fix : Break the loop by placing test constraints on the design

•Black boxes
Logics that drive and driven by black boxes are unobservable and uncontrollable respectively.
Fix : 1. Add appropriate test points around the black boxes
2. Use a test model representing the black boxes
7.What are ATPG DRC violations you faced ? How you fixed ?

■ Faced c1 violation due to clock PIs off failed to force off a clock line
■ Clock is driven by mux
■ Fixed by adding functional clk and scan en clk
8.In clock violation in clock gating circuit where will we add mux after or before?
9.what is clock gating circuit? Draw the clock gating cell and its waveform. How it is working ?
clock gating is one of the simplest and most used method to reduce the dynamic power of the design
10.what are the outputs of  scan insertion?

■ Design(Netlist)- This netlist contains the original design modified with the inserted test structure. The
output netlist format is gate_level verilog.
■  ATPG setup (Dofile and Test Procedure File) The tool can automatically create a dofile and test
procedure file that you can supply to the ATPG tool. theese files contain the circuit setup information that
you specified to tool as well as information on the thest structures that the tool inserted into the desing. the
tool create these files for you when you issue the write_atpg_setup command.
■ Test Procedure FileWhen you issue the Write Atpg Setup command, the tool writes a simpletest procedure
file for the scan circuitry it inserted into the design. You use this file with the downstream ATPG tools.

 
11.what are contents available in test procedure file?

■ How the scan circuitry within a design operates.

■ This file describes the data and order of events to operate the scan circuitry .
■ Loading and Unloading data ,Shifting data ,capture the data.
■ They contain cycle based procedures and timing definitions that tell the DFT tools how to operate
the scan structures in the design.
12.how you declare clock template in test procedure file?
13.how many test clocks and functional clocks
in your project and their frequency ?
14.what is lock up latch ? where you have inserted ? How it helps to avoid skew ? Explain with
waveform
■ A scan lock up is a retiming sequential cell on a scan path that can address skew problems
between adjacent scan cells when clock mixing or edge mixing is enabled.
15.what happens if we insert posedge flop followed by neg edge flop ?
if we place the positive flip flops first followed by negative flip flops then the data will be transfer out with in three clock cycles which is not good for a design and we might get the hold violations.
16.what is scan compression ? and what is the need of this ? How it helps in your project ?
■ • Scan compression technology uses on chip circuitry to compress the scan ATPG patterns,
without compromising the fault coverage.
 
17.what are different compression techniques ? Draw structure of compression techniques ?
18.how we reduce test time in compression? Explain with example.
19.How we reduce test date volume in compression ? Explain with example.

■ Test Data Volume ≈ Scan Cells × Scan Patterns

20.what is your compression ratio? How to decide compression ration ?

Compressio Ratio depends on

 Tester memory
 Required Coverage you have to achive
21. what happens if we increase compression ratio?

■ Contrlability and Observability will be reduced

■ Number of scan chains will increase ,test coverage will decrease
22.what is your EDT internal scan chain length? How to decide ?
ATPG FLOW
23.total no of channels in one block?
24.Which atpg simulation tool you have used ?
Modelsim
25.what is coverage you got for transition and stuck at?
26 why your transition coverage is less?
■ During transition fault coverage false path and multicycle path coverage .
■ And faults present set,reset and inputs and outputs are not able to detect through At speed testing.

27. what is upf?

 28.what is false path and multi cycle path ? explain with
example ?
A false path is a path, which exists in the chip but it would never be exercised in the operation of the chip. STA
tools can report violations on false paths because there is no knowledge of circuit function.
Multicycle path
Set up and hold violations

■ https://www.slideshare.net/DrUshaMehta?utm_campaign=profiletracking&utm_mediu
m=sssite&utm_source=ssslideview
■ Fault models
■ https://www.slideshare.net/DrUshaMehta?utm_campaign=profiletracking&utm_mediu
m=sssite&utm_source=ssslideview
■ Bist falt simulation
■ https://www.eng.auburn.edu/~strouce/elec6280.html
29.how many pulses for stuck at and transition?

■ Stuck at fault : One pulse

■ Transition fault:Based on sequential depth,
2 pulses during LOC
1 pulse during LOS

■ If there is 100 flops Stuck at require 100+1

■ For Transition 100+2
39.how to improve your coverage?
31.what is occ?
OCC is a core logic used in the design to generate launch and capture pulse. There are different
algorithms like Launch-On-Shift (LOS) and Launch-On-Capture (LOC) performed using OCC for
transition test
 32.explain the LOC and LOS with waveforms? Which is preferrable ?

Launch on last shift - In this method, during the last shift itself, we will shift in the required value in to the
flop which will create the required transition on the intended node.
Launch on capture - In this method, the flop which creates the launch on the intended node will get the value through
D path. Scan-enable will be low during this time.

Which is preferable?
If you want more coverage LOS
If
33.Adv and Disadv of LOC and LOS.

■ pros of loc :scan enable is not in timing path, supports many levels of non scan logic,timing
faults on pins of memories can be tested,supported with false and multicycle path masking
■ cons of loc: a bit more of a complex problem for pattern generation
■ pros for los :less complex patterns generation,can test through false paths
■ cons of los:scan enable mudt be routed and balanced so it transitions in time for the cpture
clock,only generates vasic combinational patterns ,some detections not possible with launch off
shift
34.what are issues you faced in atpg simulation with zero timing?
35.What is x mismatch and binary mismatch ?
■ During simulation mismatch estimated value and simulated value will be shown It will show

■ Binary mismatch
36. what are the issues you faced with
sdf simulation? How to fix it ?
37.what is setup time and hold time?

■ The required time duration that the input data MUST be stable before the triggering-edge of the
clock.
■ The required duration that the input data MUST be stable after the triggering edge of the clock.
38.how to solve setup time and hold time?

■ SETUP

Reduce the amount of buffering in the path

Replace buffers with 2 inverters place farther apart

39.what are untestable faults?
40.what will be the pattern type in ATE?

■ Chain patterns
■ Scan patterns
41.What is parallel pattern and serial pattern ? what is the difference ?
42.what is test point Insertion?
■ Test point insertion adds control points and observation points for providing additional
controllability and observability to improve the detection probability
■ A control point can be connected to a primary input, an existing scan cell output, or a dedicated
scan cell output. An observation point can be connected to a primary output through an
additional multiplexer, an existing scan cell input, or a dedicated scan cell input.
■ Whenever there is low test coverage we insert a test point as the primary input to get the control
and observe the node.
43. what all things you need to take care while/before inserting on OCC ?
44. why we don't connect the capture flop's clock to the lockup latch?
45. How you will improve transition faults test coverage?

■ By increasing abort limit coverge will increase

■ IIn real design, usually there are two typical types of logic that impact test
coverage. The first type resides in the input/output shadow parts between digital
logic and black box. The second type is in the input/output pads of un-bonded
pads in multi-die package.
46. Have you ever seen condition statements in spf and how they work?
47.What are the major issue in coverage drop ?

■ Uncontrolled and unobservable nodes in the design.

■ DRC violation can be cause of coverage drop.
■ Having non scan element in the design.
48.Convert normal flop to scanned flop. Draw structure.
49.What is Sample, preload, intest and extest instruction in boundary scan ? Draw diagram and
explain. 
50. Explain any 5 violations you got during scan Insertion and how you cleared ?
51.what are issues faced during scan insertion and how did you fixed??
52.which version you have used for scan insetion?

■ Tessent shell 2020.1

53.Size of your block ? Total gate counts and flop counts ? 
54.What are the primary inputs used during atpg ?

■ Design : The supported design data format is gate-level Verilog. Other inputs also include 1) a
cell model from the desig library and 2) a previously-saved, flattened model.
■ Test Procedure File :This file defines the operation of the scan circuitry in your design. You can
generate this file by hand, or Tessent Scan can create this file automatically when you issue
thecommand write_atpg_setup..
■ Library : The design library contains descriptions of all the cells used in the design. The tool
uses the library to translate the design data into a flat, gate-level simulation model for use by the
fault simulator and test generator.
■ Fault List: The tool can read in an external fault list. The tool uses this list of faults and their
current status as a starting point for test generation.
■ Test Patterns : The tool can read in an external fault list. The tool uses this list of faults and their
current status as a starting point for test generation
55.How you pulse different clocks during stuck-at and transition-test ? 

■ By using occ
56.How much is your targeted coverage for ac &amp; dc and how you improved coverage??
56.What is Sequential depth? How to decide it ?
57.What are Falut models ?
58.What are type of Fault class?
60.How you debugged Simulation mismatches in notiming and timing?
61.How to debug if parallel sim passing and serial sim failing??

■ Because of any non scan elements in the scan chain.

■ Sequential depth not specified properly.
62.Can we generate three cycle pattern in capture?

■ Yes we can using occ

63.How can we takecare if we have multicycle path??
64.what are the DFT activities in the project?

■ RTL verification, MBIST verification, LINT verification, DFX validation, SCAN insertion,
ATPG, BSDL
65. Total how many blocks or partitions in your project ?
66. whether all the blocks/partitions will be released in parallel ?
67. Whether all validations happen at SOC level or block level ?
68. for mbst, how many controllers and howmany algorithms.
69. How to decide number of mbist controllers ?
70. for ATPG, howmany faults types targeted for each block ?
71. if we have different clocks how do you insert the scan?
72.what is transparent latch and where we insert? Transperent latch diagram?

■ A transparent latch is a storage element. It has an input, an output, and an enable or gate pin.
When the enable is active, the output transparently follows the input (with some small delay).
When the enable becomes inactive, the output freezes
73.Draw edt logic? How Decompression & compactor how it looks?
74.How you did coverage analysis?

■ By using report_statistics command

75.What is pipeling technique ?
76.why we need mbist

■ Due to complexity of memory architectures,the possibility od occuring manufacturing defects is

more.Hence ,memoery is very challenging task.
■ Memory Built in Self test has been proven to be one of the most cost effective and widely used
solution for memory testing.
 It allows for robust testing of memories 
  Reduced test time 
  All the memories of the design can be tested in parallel 
  Lesser test cost
 
77.What are different memory faults? How MBIST controller test those faults ?
■ Stuck-at fault
■ Transition fault
■ Coupling fault

■ Neighborhood pattern sensitive fault

78.Draw mbist architecture explanation?
79.What are the connections between mbist controller and memory’s ?
80. how many blocks in your SOC ?
- 30 blocks.
81. how many blocks you worked ?
- 3 blocks.
82. what is Total flop count and gate count in your designs ?
- you can say flop count >80k. Don't say 15k, 20k
- gate count around 1.5 million
83. how many testclock and functional clocks in your blocks and their frequency ?
- 1 testclock (20mhz)
- 4 to 6 functional clocks (500mhz to 1ghz)
84. how many scan channels, internal scan chains, compression ratio
- 4 to 8 scan channels
- 10 compression ratio
- internal chains = scan channels x compression ratio
85. How you generate capture clock for stuck-at test ?
- From IO pad
86. How you generate capture clock for transition test ?
- From OCC
- 87. Consider total 5 clocks in your design. Draw waveform for Stuck-at test
- - Refer OCC paper in link question 31. It will be pulse in staggered manner.
- 88. Consider total 5 clocks in your design. Draw waveform for transition test
- - each clock pulsed per capture
- 89. Is there dedicated test clock in your design ?
- - yes
90.Different types of atpg fault models ? how you test a sutck-at 0/1 in AND gate. Do it for other
gates as well
91. Simulation mismatches in zero delay Simulation and sdf simulation? How you resolved ?
- zero delay simulation : clock issue, reset issue, TDR programming issue
- SDF simulation : setup and hold issue, SDC missing constraints issue
92. How you find frequency from waveform. from where to where you measure?
- between one pulse posedge to next pulse posedge
93. Whether stuck-at faults can be tested during transition test ? if yes, how much stuckat coverage you achieved during
transition test?
- yes, In atpg dofile we have to enable stuck-at faults = yes and transition faults = yes
- stuck-at coverage achieved 80% during transition test
94. Different between test coverage and fault coverage?
95.How many tests you run for atpg ? What is Sequence ?
1 transition (with compression enable), 3 stuck-at (with compression with clock-gate enable,
compression with clock-gate disable, fullscan)
96 .what is memory shadow logic in scan insertion ?
DFT shadow logic is recommended to increase the testability of logic around modules for which the ATPG
tools cannot generate test patterns. Shadow logic adds the ability to
(i) Observe the data on the nets connected to the inputs of the untestable logic
(ii) Control the nets connected to the outputs of the untestable logic
There are two ways to insert shadow logic:
1 ) Manually Inserting DFT Shadow Logic
The manual method supports insertion of bypass logic and scannable logic with or without register sharing.
2) Automatically Inserting DFT Shadow Logic
The automatic method only supports insertion of scannable logic without register sharing.
97.what is Ramseqential pattern
98.How many test patterns required to test stuck at faults in AND gate ?

■ For a single-output, n-input gate, there are 2(n+1) possible stuck-at errors. In
this case, with n=2, six stuck-at errors are possible.
99.How many test patterns required to test transition faults in AND gate ?
00,11 a-s-0,b-s-0,c-s-0
11,00 a-s-1,b-s-1,c-s-1

100.Howmuch fault coverage you achieved ?

-Coverage 85% for transition and 99% for stuck-at.

101. Total pattern count for stuck-at and transition test ?

around 1000 patterns for stuck-at and 500 patterns for transition
102. structure of Decompressor and compression logic used in your block.
Verification vs. Test
■ Verifies correctness of design. ■ Verifies correctness of manufactured
hardware.
■ Performed by simulation,
hardware emulation, or formal ■ Two-part process:
methods. – 1. Test generation: software process
■ Performed once prior to executed once during design
manufacturing. – 2. Test application: electrical tests
■ Responsible for quality of applied to hardware
design. ■ Test application performed on every
manufactured device.
■ Responsible for quality of devices.

Copyright 2001,
Agrawal & VLSI Test: Lecture 1 125
■ CAN HOLD VIOLATION BE REMOVED AFTER CHIP WAS
FABRICATED
■ September 18, 2019 vlsi space BLOG Leave a comment
■ Can we remove the hold violation once the chip was out from
fabrication unit?
After the chip was manufactured, if there are any setup
violations in the design, can removed by reducing the clock
frequency of the design at the cost of device performance.Now
if the hold violation was found after chip was out,we have to
discard the the chip. Theoretically there are few methods to
remove the hold violations, but in practical cases these may not
be implemented on the chip
1. By reducing the supply voltage and frequency, we can increase
the delay of the cell and thus meet the hold violations
2. By increasing the temperature, propagation delay of the cell
decreases and thus we can met the hold violation. However for
65nm and below technology, temperature inversion
phenomena was observed and thus delay decreases as
temperature increased. For lower technology nodes increasing
the temperature worsens the hold timing.
SETUP TIME AND HOLD TIME
September 29, 2019  vlsi space BLOG Leave a comment
Any digital design should be free from setup and hold violation. First, we will understand what is Setup and Hold time. Below fig is simple circuit with launch
and capture flipflop, these are ideal flip flop (means setup time and hold time are zero)

             
Hold Slack is the difference between the Arrival time and the required time of the data signal.
During the Hold calculation we must take min delay values in data path and max values in
clock path and the hold slack must be greater than zero for violation free circuit. Hold check is
done on same clock edge
Hold Slack =AT-RT
RT= clock_period(tp)+clock_network_delay(tc)+hold_time(th)
AT=flip_flop_delay(tc2q) +wire_delay(tw)+comb_delay(td)
Note: As hold analysis is carried on same clock, we must make clock_period to zero(tp=0)
How to we overcome the setup or hold violation
Setup violation occurs when the data arrives late at the capture flip flop and this can be
avoided by reducing the delay in the data path. Delay in data path can be reduced in different
steps
•LVT cells offers less delay, we can swap the HVT cells to LVT cells
•High drive strength cells delay is less compared to low drive strength and we can swap
between the low drive strength cell to high drive strength cell, but we need compromise with
the power.
•If we can comprise with speed of the design, then clock frequency can be reduced to avoid the
setup violation.
Hold violation occurs when the data arrives early at the capture flip flop and we need add
delays in the data path to avoid the hold violation. We can do any of the steps to increase the
delay in the data path    
•We need to add the buffers in the data path
•Swap HVT cells to LVT cells
• Swap high drive strength cells to low drive strength cells
http://www.uuudoc.com/doc/ab/jdae/ag/fgadaai-bjcgicehg.html
What is a Time Plate?
Time plate defines the single tester cycle and specifies all the
events placed in cycle. All
clocks must be defined in the time plate definition.
Timeplate gen_aman =
https://www.eetimes.com/designs-with-multiple-clock-domains-
new-tools-avoid-clock-skew-and-reduce-pattern-counts/
Let's say there is a chain with 8 flops and one of them has a hold viol. Assuming you've enough data patterns to fill in other chains
1. Shift
to find the captuting failure. How in
willall
you1 do?
to initialize
OR How youthefigure
chain.
out which is bad flop?
2. You shift in 00001111(right bit first, left bit last) and if the
capture fails.
The cause of failure should be in the 1st 4 flops because the
data in the
2nd half is not supposed to change and should have no effect on
the
capture failure.
3. shift in all 1 to initialize the chain.
4. You shift in 00111111 and the capture passes. The cause of
failure
should be in the 3rd or 4th flops because the 3rd and 4th flops
are only
flops that change the value and can contribute to the capture
failure.
5. shift in all 1 to initialize the chain,
6. You shift in 00011111 and the capture fails. The the cause of
failure
should be in the 3rd flop
Top 5 Solutions for Optimal DFT (Design for Testability) in Lower Technology Nodes

https://www.einfochips.com/blog/top-5-solutions-for-optimal-
dft-design-for-testability-in-lower-technology-nodes/
http://cc.ee.ntu.edu.tw/~cmli/VLSItesting/