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Book-1 Chapter-5 Internal Memory

This chapter discusses internal memory, including semiconductor memory types like DRAM and SRAM. It covers memory cell operation, dynamic and static RAM structures, ROM types, chip packaging, module organization, and interleaved memory. The chapter also explains error correction using Hamming codes and discusses advanced DRAM organizations like SDRAM, RDRAM, and DDR SDRAM that improve memory interface performance.

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49 views26 pages

Book-1 Chapter-5 Internal Memory

This chapter discusses internal memory, including semiconductor memory types like DRAM and SRAM. It covers memory cell operation, dynamic and static RAM structures, ROM types, chip packaging, module organization, and interleaved memory. The chapter also explains error correction using Hamming codes and discusses advanced DRAM organizations like SDRAM, RDRAM, and DDR SDRAM that improve memory interface performance.

Uploaded by

a ahmad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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+

Chapter 5
Internal Memory
+
Memory Cell Operation
Semiconductor Memory Types

Table 5.1 Semiconductor Memory Types


+
RAM Technologies

 RAM is constructed using following two technologies:


 Dynamic RAM (DRAM)
 Static RAM (SRAM)
+
Dynamic RAM (DRAM)

 DRAM

 Made with cells that store data as charge on capacitors

 Presence or absence of charge in a capacitor is interpreted


as a binary 1 or 0

 Requires periodic charge refreshing to maintain data storage

 The term dynamic refers to tendency of the stored charge to


leak away, even with power continuously applied
+
Dynamic
RAM
Structure

Figure 5.2a
Typical Memory Cell Structures
+
Static RAM
(SRAM)
 Digital device that uses the same
logic elements used in the
processor

 Binary values are stored using


traditional flip-flop logic gate
configurations

 Will hold its data as long as power


is supplied to it
+
Static
RAM
Structure

Figure 5.2b
Typical Memory Cell Structures
SRAM versus DRAM
SRAM
 Both volatile
 Power must be continuously supplied to the memory
to preserve the bit values

 Dynamic Cell
Simpler to build, smaller in size
DRAM

 More dense (smaller cells = more cells per unit area)


 Less expensive
 Requires the supporting refresh circuitry
 Tend to be favored for large memory requirements
+  Used for main memory

 Static Cell
 Faster
 Used for cache memory (both on and off chip)
+
Read Only Memory (ROM)
 Contains a permanent pattern of data that cannot be changed or
added to

 No power source is required to maintain the bit values in memory

 Data or program is permanently in main memory and never needs


to be loaded from a secondary storage device

 Data is actually wired into the chip as part of the fabrication


process
 Disadvantages of this:
 No room for error, if one bit is wrong the whole batch of ROMs must
be thrown out
 Data insertion step includes a relatively large fixed cost
+
Programmable ROM (PROM)

 Less expensive alternative

 Nonvolatile and may be written into only once

 Writing process is performed electrically and may be performed by


supplier or customer at a time later than the original chip fabrication

 Special equipment is required for the writing process

 Provides flexibility and convenience

 Attractive for high volume production runs


Read-Mostly Memory

EEPRO Flash
EPROM
M Memory
Electrically Erasable
Programmable Read-Only Intermediate between
Erasable Programmable
Memory EPROM and EEPROM in
Read-Only Memory
both Cost and Functionality

Can be written into at any


time without erasing prior
contents
Uses an electrical erasing
Erasure process can be
technology, does not
performed repeatedly
Combines the advantage of provide byte-level erasure
non-volatility with the
flexibility of being
updatable in place
More expensive than PROM Microchip is organized so
but it has the advantage of that a section of memory
the multiple update More expensive than cells are erased in a single
capability EPROM action or “flash”
Typical 16 Mb DRAM (4M x 4)
Chip Packaging
Figure 5.5

256-KByte
Memory
Organization

+
1MByte Module Organization
Interleaved Memory Composed of a collection of
DRAM chips

Grouped together to form a


memory bank

Each bank is independently


able to service a memory
read or write request

K banks can service K


requests simultaneously,
increasing memory read or
write rates by a factor of K
If consecutive words of
memory are stored in
different banks, the transfer
of a block of memory is
speeded up
+
Error Correction
 Hard Failure
 Permanent physical defect
 Memory cell or cells affected cannot reliably store data but become stuck at
0 or 1 or switch erratically between 0 and 1
 Can be caused by:
 Harsh environmental abuse
 Manufacturing defects
 Wear

 Soft Error
 Random, non-destructive event that alters the contents of one or more
memory cells
 No permanent damage to memory
 Can be caused by:
 Power supply problems
 Alpha particles
Error Correcting Code Function
+
Hamming
Error
Correcting
Code
+
SEC and DED Requirements
+
Layout of Data Bits and Check Bits
Check Bit Calculation
+
Hamming SEC-DED Code
Advanced DRAM Organization SDRAM

 One of the most critical system bottlenecks when using high-


performance processors is the interface to main internal memory
DDR-DRAM
 The traditional DRAM chip is constrained both by its internal
architecture and by its interface to the processor’s memory bus

 A number of enhancements to the basic DRAM architecture have


been explored:
RDRAM

Table 5.3 Performance Comparison of Some DRAM Alternatives


+ Summary Internal
Memory
Chapter 5

 Semiconductor main memory


 Hamming code
 Organization
 DRAM and SRAM  Advanced DRAM organization
 Types of ROM  Synchronous DRAM
 Chip logic  Rambus DRAM
 Chip packaging  DDR SDRAM
 Module organization  Cache DRAM
 Interleaved memory
 Error correction
 Hard failure
 Soft error

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