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Design Process & Soc: M1: Introduction To Embedded Systems

The document discusses the design process for embedded systems including challenges, the need for optimization of performance, cost, power and interfaces. It also discusses system on chip design, use of FPGA cores, and an example non-contact smart card system on chip architecture.

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Pooja S
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0% found this document useful (0 votes)
39 views8 pages

Design Process & Soc: M1: Introduction To Embedded Systems

The document discusses the design process for embedded systems including challenges, the need for optimization of performance, cost, power and interfaces. It also discusses system on chip design, use of FPGA cores, and an example non-contact smart card system on chip architecture.

Uploaded by

Pooja S
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Design Process & SoC

M1: Introduction to Embedded Systems


Challenges in ESD
 How much h/w is required?
 How do we meet deadlines?
 How do we minimize power consumption?
 How do we design for upgradeability ?
 Does it work?
 Complex Testing
 Limited observability and controllability
 Restricted Development Environment

Embedded System Design - RL1.3.1 © K.R.Anupama & Meetha.V.Shenoy 2


Embedded System Design
Process
 Design method - Optimize performance
 Tools for ESD
 Split-up design work
 Process has to optimise
 Manufacturing cost
 Performance
 Power Consumption
 User I/f

Embedded System Design - RL1.3.1 © K.R.Anupama & Meetha.V.Shenoy 3


Requirements Every step
Analyze
Refine
Specifications Top Down
Verify
Approach

Architecture

Components

Sys Integration

Embedded System Design - RL1.3.1 © K.R.Anupama & Meetha.V.Shenoy 4


SoC
 Generally final step in Embedded System Design

Embedded System Design - RL1.3.1 © K.R.Anupama &


5
Meetha.V.Shenoy
Embedded System –on –Chip
 Embedding an GPP
 ARM7,ARM9 + Special Circuits

Embedded System Design - RL1.3.1 © K.R.Anupama & Meetha.V.Shenoy 6


FPGA Cores
 Large no. of programmable gates
 Set of gates - Macro Cell
 Each cell - several i/p / several o/p
 All cells inter connect - Arrays
 Algo FT, IFT, LT, ILT, encryption/ decryption, DCT

Embedded System Design - RL1.3.1 © K.R.Anupama & Meetha.V.Shenoy 7


SoC – Non Contact Smart Card
RAM ROM EEPROM

ASIP

Timer/Int I/o I/f

FSK Mod

Charge Pump Antenna

Embedded System Design - RL1.3.1 © K.R.Anupama & Meetha.V.Shenoy 8

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