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Low Power Techniques For SRAM

Low power techniques for SRAM include using a 6T CMOS SRAM cell which draws little static power, pulsing wordlines and isolating sense amplifiers from bitlines after sensing to reduce bitline swings and power. Techniques also involve limiting bitline voltages during reads and writes, such as swinging bitlines from 0V to 1V during writes instead of the full supply voltage range, and precharging bitlines to 0.5V during reads before limiting the swing. Reducing the wordline voltage during reads can restore stability if lowering the write voltage impacts cell ratios.

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212 views

Low Power Techniques For SRAM

Low power techniques for SRAM include using a 6T CMOS SRAM cell which draws little static power, pulsing wordlines and isolating sense amplifiers from bitlines after sensing to reduce bitline swings and power. Techniques also involve limiting bitline voltages during reads and writes, such as swinging bitlines from 0V to 1V during writes instead of the full supply voltage range, and precharging bitlines to 0.5V during reads before limiting the swing. Reducing the wordline voltage during reads can restore stability if lowering the write voltage impacts cell ratios.

Uploaded by

deberjeet usham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Low Power Techniques for SRAM

What is SRAM Memory?


4T SRAM Cell

to reduce the amount of


standby current, a high-
valued load resistor is.
Thus, there is a trade-off
between the high resistance
required for low power and
the requirement to provide
wider noise margins and
high speed.

So..
CMOS 6T SRAM
• CMOS static power dissipation is lowest; essentially,
it is limited by the leakage current
• A CMOS memory cell thus draws current from the
power supply only during a switching transition.
• Other advantages of CMOS SRAM cells include high
noise immunity due to larger noise margins, and the
ability to operate at lower power supply voltages
• the area disadvantage of the CMOS SRAM cell has
been reduced significantly (discussed in further
slides).
Each cell lies at the intersection of a particular wordline and
bitline, which can be used to "address" it. The data in the cells
is read or written by the same bit-lines
• The small signal difference on bit line is amplified
• There is 1 SA per column, so its transistor size can
be increased
Sense amplifier

V+dV
V-dV
BL
BL_bar

sense
• A sense amplifier is part of SRAM that is used when
data is read from the memory; its role is to sense the
low power signals from a bitline that represents a data
bit (1 or 0) stored in a memory cell, and amplify the
small voltage swing to recognizable logic levels so
the data can be interpreted properly by logic outside
the memory
• SA allows the storage cells to be small, since each
individual cell need not fully discharge the bit line.
• SA also helps to deal with area constraint faced by
CMOS SRAM
“Techniques for power reduction”
• In a conventional SRAM
design, the bitlines are
allowed to swing from
rail to rail during a read
operation.
• To conserve power, the
voltage swing at the
bitlines needs to be
limited.
• One way to achieve this
is to isolate the memory
cells from the bitlines
after a successful
differential sensing.
• This prevents the
memory cells from
changing the bitline
voltage further.
• pulsed signals at the wordlines and the sense
amplifiers
• the bitline sense amplifiers also need to be
isolated from the bitlines after sensing.
• This prevents the bitline capacitance from having
large voltage swing, thus saving power.
The generation of
wordline pulses is very
critical because if the
pulses are too short, the
sense operations may
fail. On the other hand if
the pulses are too long,
the power efficiency is
degraded because the
bitline swing depends on
the duration of the
pulses.
A simple technique is to
use delay lines to
generate pulses with a
fixed width.
• In SRAM sense amplifier design, the amplifier may
swing the bitlines after the cell access transistors have
been turned off.
• A method to solve this problem is to use bitline
isolation technique
• After a sufficient differential voltage has developed
on the bitlines, the isolate signal is asserted to isolate
the sense amplifier from the bitlines.
• This prevents the sense amplifier from further
swinging the bitline capacitance.
• The isolate and sense signals need to be timed
properly to balance the trade-off among noise
immunity, power dissipation and sensing delay.
Operation
• reduce bitline differential voltage from (0V, 5V) to (OV, I
V) during the write cycles to reduce the write power.
• The suppressed bitline voltage resulted in reduced
transistor size βn in the SRAM cell to allow successful
write operations. This caused a read instability problem in
the SRAM cell.
• The problem was eventually solved by reducing the
wordline voltage to 3V during the read operations and a
regular 5V wordline voltage during the write operations.
• The usual pulsed wordline technique was used to limit
bitline swing during read cycles.
• standard 5V system with a 6-transistor CMOS SRAM
cell.
• reduce the bitIine differential voltage during the write
cycles to (0V, 1V).
• During the precharge cycles for read, the bitlines are
precharged to 0.5V.
• In the sensing stage of the read cycles, the bitline voltage
swing is limited by disabling the access transistors as
soon as the bitline voltage difference is sufficient for
sensing.
• The bitline voltage swing is thus limited to less than IV
during operation.
• Since bitline capacitance is large and the SRAM has a
wide word length, the power reduction from the limited
read and write voltage swing technique is substantial.
• use of the non-traditional (0V, I V) write-voltage on the
bitlines posed a problem in the SRAM cell design
• In an SRAM cell design, the transistor size ratio βw/(βn
+ βp ) needs to be kept below a certain threshold to
maintain the read stability.
• The reduction of write differential voltage to (0V, I V)
prompted the designer to reduce βn in order to
guarantee successful write operations
• caused read
• By reducing the wordline voltage of the access
transistors from 5V to 3V during read.
• This essentially restored the read stability lost.
• The wordline voltage remained at 5V during the write
cycles.
Thank You.

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