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VHDL Digital Logic: 2nd Class

The document discusses VHDL digital logic and fundamentals. It covers VHDL units like library declarations, entity declarations, architecture and port modes. It also provides examples of coding a NAND gate, 4-to-1 MUX and use of WHEN/ELSE and WITH/SELECT/WHEN statements.

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abdolrahman altamime
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20 views23 pages

VHDL Digital Logic: 2nd Class

The document discusses VHDL digital logic and fundamentals. It covers VHDL units like library declarations, entity declarations, architecture and port modes. It also provides examples of coding a NAND gate, 4-to-1 MUX and use of WHEN/ELSE and WITH/SELECT/WHEN statements.

Uploaded by

abdolrahman altamime
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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VHDL Digital Logic

2nd Class
VHDL is a high-level hardware description
language used to describe the behavior of
digital circuits or system.
VHDL Fundamentals
Fundamental VHDL Units
A standalone piece of VHDL code is composed
of at least three fundamental sections
Library declarations
Library declarations: Contains a list of all
libraries to be used in the design, For example:
EEE is a commonly used standard library

The common packages in IEEE are Std_logic_1164 and Std_logic_arith


Library declarations - syntax

EX
Entity declaration
Entity Declaration describes the interface of the component, i.e. input
and output ports
Port Modes
• In: Data comes in this port and can only be read within the entity. It can
appear only on the right side of a signal or variable assignment.

• Out: The value of an output port can only be updated within the entity. It
cannot be read. It can only appear on the left side of a signal assignment.

• Inout: The value of a bi-directional port can be read and updated within
the entity model. It can appear on both sides of a signal assignment.
Entity Declaration
Architecture – simplylified syntax
Architecture
Describes an implementation of a design entity.
Architecture example
Entity Declaration & Architecture
nand_gate.vhd
Class work:
Write a complete VHDL code to construct the circuit, as shown in
figure below.
Soluti
on
Concurrent Code
WHEN (Simple and Selected)
WHEN is one of the fundamental concurrent. It appears in
two forms:
 WHEN / ELSE (simple WHEN).
 WITH / SELECT / WHEN (selected WHEN).
WHEN / ELSE – simplylified syntax
WITH / SELECT / WHEN – simplified syntax
4 to1 Mux Example
Construct a 4-to-1 Mux circuit, as shown in figure below
Solution with WHEN/ELSE
Second Solution using WITH/SELECT/WHEN
Comparators

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