Digital Adder Circuits: A Review of Power,

Delay, Area, and Transistor Count

Authored By:
Prabhanshu Kumar, Deepak Kumar Sharma, Sushivam, Shivangi Barthwal, and
Brijesh Kumar
Presented By:
Deepak Kumar Sharma,

Graphic Era University, Dehradun, Uttarakhand

ICRTMSCA, 2022, Paper ID- 9661

JULY 15, 2022

 Presentation Outline
• Introduction

• Power Consumption

• Delay

• Area

• Transistor Count

• Conclusion

• References

2
 Introduction

• Microprocessors are a fundamental and essential part of many electronics chips.

• Adder is part of ALU.

• Perform arithmetic and logical operations in the processor.

• Adders are used as a major computing circuit for digital designs.

• For performing the high computational tasks, adders should be very advanced.

• Structure of the Adder circuit plays an important role in its functioning.

• It should consume low power, have high speed, and have a lesser Transistor count.

3
 Power Consumption

• Power consumption is the amount of

energy used per unit time.

• The power consumed in a device is

composed of two types – dynamic,

static

• Recent development in circuits has

resulted in different technologies of

fabrication for reducing power

consumptions.

4
 Delay

• Time to stabilize the output of the

circuit.

• The delay time depends on the size

and number of transistors.

• The comparison of delay of all the full

adders are shown in this table.

• New techniques like GDI, CMOS,

CNFETs, and many more techniques

are used that reduce the delay.

5
 Area

• Size of the Adder circuit.

• Nanotechnology provides us a new

prospect for computing.

• At present the transistors are

getting very compact, so the

probability of making them even

smaller is a quite tough task.

• A comparison of area

(nanotechnology) of different full

adders is undertaken.
6
 Transistor Count

• In recent days, VLSI and SLSI circuits

methodology are used in portable

devices.

• Reduce the number of transistors so as

to put more devices on a single silicon

chip by reducing its area.

• Smaller number of transistors

consumes less power.

• Transistor count is a primary concern

that affects the design and complexity of

7
adder circuits.
 Conclusion
Conclusion:
• We concluded that there are vast strategies to implement full adder
circuits each with its own merits and demerits.
• We have to choose different adder circuit on the basis of
performance.

8
 References

1. B. Shrivathsa, V. G. K. Kumar and Nisha, International Journal of Engineering

Research & Technology (IJERT) 7, 2278-0181, (2018).

2. J. Kahlon, P. Kumar, A. Garg, and A. Gupta, 2016 International Conference on

Advances in Computing, Communications and Informatics (ICACCI, Jaipur, India,

2016), 2121-2125.

3. J. N. Reddy, M. Tiwari, and V. P. Reddy, Turkish Journal of Computer and

Mathematics Education (TURCOMAT) 12, 1342-1347 (2021).

4. J. K. Saini, A. Srinivasulu, and R. Kumawat, Solid State Electronics Letters

(SSEL) 2, 67-78 (2020).

5. A. M. Vali‑Nasab, A. Mir, and R. Talebzadeh, Optical and Quantum Electronics

53, 1-14 (2019).

 References

6. J Rani, and A. K. Nishad, 2018 Second International Conference on Intelligent

Computing and Control Systems (ICICCS, Madurai, India, 2018), 1938-1942.

7. S. Angizi, Z. He, R. F. DeMara, and D. Fan, 2017 18th International Symposium

on Quality Electronic Design (ISQED, Santa Clara, CA, USA, 2017), 391-396.

8. M. H. Moaiyeri, M. Nasiri, and N. Khastoo, Engineering Science and Technology,

an International Journal 19, 271-278 (2016).

9. H. R. Naghizadeh, M. S. Moghadam, S. I. Tous, and A. Golmakani, International

Journal of Computing and Digital Systems 2, 47-52 (2013).

10. S. Sahani, and B. Chourasia, International Journal of Scientific Research &

Engineering Trends 6, 2790-2794 (2020).

10
 References
11. S. Tajasob, M. Rezaalipour, and M. Dehyadegari, Microelectronics Journal 89, 41-

55 (2019).

12. M. M. Basha, K. V. Ramanaiah, and P. R. Reddy, VLSI design: Circuits, System

and Applications, 469, 135-140 (2018).

13. L. S. Jie and S. H. Ruslan, “A 4-bit CMOS Full Adder of 1-bit Hybrid 13T Adder

With A New SUM Circuit”, in 2016 IEEE Student conference on Research And

Development (Kuala Lampur, Malaysia, 2016), 1-5.

14. I. Gassoumi, L. Touil, and A. Mtibaa, Journal of Electrical and Computer

Engineering, 2021, 1-9 (2021).

15. B. S. Premananda, A. Bajpai, G. Shakthivel, and A. R. Anurag, Indian Journal of

Science and Technology 14, 776-786 (2021). 11

 References

16. M. S. Kumar, S. Inthiyaz, M. Parvez, P. C. Chowdary, M. B. Kiran, and P. K.

Khan, Journal of Physics 1804, 012186 (2021).

17. M. Raj, L. Gopalakrishnan, and S. B. Ko, International Journal of Electronics

Letter 2020, 2168-1732 (2020).

18. K. Bagyalakshmi, and M. Karpagam, Journal of Microprocessor and

Microsystem 76, 0141-9331 (2020).

19. L. Liu, L. Zheng, G. Wang, Y. Shen, and Y. Liang, IEEE Acccess 7, 43691-43696

(2019).

20. F. Farzaneh, R. F. Mirzaee, and K. Navi, Journal of Computational Electronics

18, 364-373 (2019).

12
 References

21. M. A. Valashani, M. Ayat, and S. Mirzakuchaki, Microelectronics Journal 74, 49-

59 (2018).

22. T. Sharma and L. Kumre, Advances in Data and Information Sciences 38, 105-

114 (2018).

23. Y. Z. Barughi and S. R. Heikalabad, International Journal of Theoretical Physics

56, 2848–2858 (2017).

24. A Roohi, R Zand, D. Fan and R. F. DeMara, IEEE Transactions on Computer-

Aided Design of Integrated Circuits and Systems 36, 2134-2138 (2017).

25. E. Taherkhani, M. H. Moaiyeri and S. Angizi, Optik - International Journal for Light

and Electron Optics 142, 557-563 (2017).

13
 References

26. P. Kumar and R. K. Sharma, Engineering Science and Technology, an

International Journal 19, 559-565 (2016).

27. P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar and A. Dandapat, IEEE

Transactions on Very Large Scale Integration (VLSI) 23, 2001-2008 (2015).

28. Tejinder Singh, rXiv:1506.06735v1 [cs.ET], 2015.

29. S. Mukherjee, A. Jana, and S. K. Sarkar, Computational Lecture Notes in

Electrical Engineering book series 335, 375-381 (2015).

30. Q. An, L. Su, J. O. Klein, S. L. Beux, I. O’Connor, and W. Zhao, International

Symposium on Nanoscale architecture (Boston, MA, USA, 2015), 163-168.

14
15