Digital Logic Design

- Sequential Logic Circuit

Instructor: Dr. Chandan Kumar

School of Electrical and Electronics Engineering
School of Bioengineering
VIT Bhopal University
Introduction to Digital Logic Design
 Suggested Textbooks:
 M. Morris R. Mano and Michael D. Ciletti , “Digital Design
With an Introduction to the Verilog HDL”,6th Edition,
Prentice Hall of India Pvt. Ltd., 2014.
 Stephen Brown and ZvonkoVranesic, “Fundamentals of
Digital Logic with Verilog Design”, Third Edition, McGraw-
Hill Higher Education, 2013.

 Other sources
 Lecture notes
 Handouts
 Blogs
 MOOC courses
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Combinational Circuits
 The output of combinational circuit at any instant of time,
depends only on the levels present at input terminals.
 The combinational circuit do not use any memory. The
previous state of input does not have any effect on the
present state of the circuit.
 A combinational circuit can have an n number of inputs
and m number of outputs.

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Sequential Circuits
 Unlike Combinational Logic circuits that change state depending
upon the actual signals being applied to their inputs at that time,
Sequential Logic circuits have some form of inherent “Memory” built
in.
 The output state of a “sequential logic circuit” is a function of the
following three states, the “present input”, the “past input” and/or the
“past output”. 
 Sequential logic circuits are generally termed as two state or
Bistable devices which can have their output or outputs set in one of
two basic states, a logic level “1” or a logic level “0” and will remain
“latched” (hence the name latch) indefinitely in this current state or
condition until some other input trigger pulse or signal is applied
which will cause the bistable to change its state once again.

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Sequential Circuits
 The word “Sequential” means that things happen in a “sequence”,
one after another and in Sequential Logic circuits, the actual clock
signal determines when things will happen next.
 Simple sequential logic circuits can be constructed from
standard Bistable circuits such as: Flip-flops, Latches and Counters 

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Comparison
Combinational Circuits Sequential Circuits
Outputs depend only on present Outputs depend on both present
inputs. inputs and present state.

Feedback path is not present. Feedback path is present.

Memory elements are not

required. Memory elements are required.

Clock signal is not required. Clock signal is required.

Easy to design. Difficult to design.

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Types of Sequential Circuits
Asynchronous sequential circuits
 If some or all the outputs of a sequential circuit do not
change affect with respect to active transition of clock signal, then
that sequential circuit is called as Asynchronous sequential
circuit.
 That means, all the outputs of asynchronous sequential circuits do
not change affect at the same time.
Synchronous sequential circuits
 If all the outputs of a sequential circuit change affect with respect to
active transition of clock signal, then that sequential circuit is called
as Synchronous sequential circuit.
 That means, all the outputs of synchronous sequential circuits
change affect at the same time.

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Clock Signal and Triggering
Clock signal
 Clock signal is a periodic signal and its ON time and OFF time need
not be the same. We can represent the clock signal as a square
wave, when both its ON time and OFF time are same.

 The reciprocal of the time period of clock signal is known as

the frequency of the clock signal.
 All synchronous circuits are operated with clock signal. So, the
frequency at which the sequential circuits can be operated
accordingly the clock signal frequency has to be chosen

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Types of Triggering
.;
 There are two levels, namely logic High and logic Low in clock
signal. Following are the two types of level triggering.
 Positive level triggering
 Negative level triggering
Edge triggering
 There are two types of transitions that occur in clock signal. That
means, the clock signal transitions either from Logic Low to Logic
High or Logic High to Logic Low. Following are the two types of
edge triggering based on the transitions of clock signal.
 Positive edge triggering
 Negative edge triggering

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Level Triggering
 If the sequential circuit is operated with the clock signal when it is
in Logic High, then that type of triggering is known as Positive
level triggering. It is highlighted in below figure.

 If the sequential circuit is operated with the clock signal when it is

in Logic Low, then that type of triggering is known as Negative
level triggering. It is highlighted in the following figure.

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Edge triggering
 If the sequential circuit is operated with the clock signal that is
transitioning from Logic Low to Logic High, then that type of
triggering is known as Positive edge triggering. It is also called as
rising edge triggering.

 If the sequential circuit is operated with the clock signal that is

transitioning from Logic High to Logic Low, then that type of
triggering is known as Negative edge triggering. It is also called as
falling edge triggering.

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Storage elements: Latches
 A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is delivered
to the circuit), until directed by an input signal to switch states.

 Storage elements that operate with signal levels (rather than signal transitions) are
referred to as latches ; those controlled by a clock transition are flip-flops.
 Level sensitive devices

 SR latch

 The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, and two
inputs labeled S for set and R for reset.

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Difference b/w Latches and Flip
flops

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SR Flipflop
 The SR flip-flop, also known as a SR Latch, can be considered as
one of the most basic sequential logic circuit possible.
 This simple flip-flop is basically a one-bit memory bistable device
that has two inputs, one which will “SET” the device (meaning the
output = “1”), and is labelled S and one which will “RESET” the
device (meaning the output = “0”), labelled R.
 The term “Flip-flop” relates to the actual operation of the device, as
it can be “flipped” into one logic Set state or “flopped” back into the
opposing logic Reset state.

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Working
The Set State
 If the input R is at logic level “0” (R = 0) and input S is at logic level

“1” (S = 1), the NAND gate Y has at least one of its inputs at logic
“0” therefore, its output Q must be at a logic level “1”.
 Output Q is also fed back to input “A” and so both inputs

to NAND gate X are at logic level “1”, and therefore its

output Q must be at logic level “0”.
Reset State
 If the input R is at logic level “1” (R = 0) and input S is at logic level

“1” (S = 1), Q is at logic level “0”, (not Q = “0”) its inverse output
at Q is at logic level “1”, (Q = “1”), and is given by R = “1” and S =
“0”. As gate X has one of its inputs at logic “0” its output Q must
equal logic level “1” (again NAND gate principles). Output Q is fed
back to input “B”, so both inputs to NAND gate Y are at logic “1”,
therefore, Q = “0”.

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D Flip-flops
 The D Flip Flop is by far the most important of the
clocked flip-flops as it ensures that ensures that inputs S
and R are never equal to one at the same time.
 The D-type flip flop are constructed from a gated SR flip-
flop with an inverter added between the S and
the R inputs to allow for a single D (Data) input.

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D Flip-flops
 D flip flop is a better alternative that is very popular with
digital electronics. They are commonly used for counters
and shift-registers and input synchronization.
 In a D flip flop, the output can be only changed at the
clock edge, and if the input changes at other times, the
output will be unaffected.

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 Truth table : A truth table shows how a logic
circuits output responds to various
combination of inputs
 Characteristics Table : it defines the next
state of flip-flop in terms of flip-flop input and
current state.
 Excitation Table: it defines the flip-flop input
variable as function of the current state and
next state.

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JK Flip-flops
 The basic S-R flip-flop circuit has many advantages and uses in
sequential logic circuits but it suffers from two basic switching
problems.
 the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
 if Set or Reset change state while the enable (EN) input is high the
correct latching action may not occur
 Then to overcome these two fundamental design problems with the
SR flip-flop design, the JK flip Flop was developed.
 This simple JK flip Flop is the most widely used of all the flip-flop
designs and is considered to be a universal flip-flop circuit.
 The two inputs labelled “J” and “K” are autonomous letters chosen
by its inventor Jack Kilby to distinguish the flip-flop design from
other types.

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JK Flip-flops
 The sequential operation of the
JK flip flop is exactly the same
as for the previous SR flip-flop
with the same “Set” and “Reset”
inputs.
 The difference this time is that
the “JK flip flop” has no invalid
or forbidden input states of the
SR Latch even when S and R
are both at logic “1”.

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Race Around Condition - JK Flip-
flop
 For J-K flip-flop, if J=K=1, and if CLK=1 for a long period
of time, then Q output will toggle as long as CLK is high,
which makes the output of the flip-flop unstable or
uncertain.
 This problem is called race around condition in J-K flip-
flop.
 This problem (Race Around Condition) can be avoided
by ensuring that the clock input is at logic “1” only for a
very short time.
 This introduced the concept of Master Slave JK flip flop.

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The Master-Slave JK Flip Flop
 JK flip-flops suffers from timing problems called “race” if the output
Q changes state before the timing pulse of the clock input has time
to go “OFF”. To avoid this the timing pulse period ( T ) must be kept
as short as possible (high frequency). 
 The Master-Slave Flip-Flop is basically two gated SR flip-flops
connected together in a series configuration with the slave having
an inverted clock pulse. The outputs from Q and Q from the “Slave”
flip-flop are fed back to the inputs of the “Master” with the outputs of
the “Master” flip flop being connected to the two inputs of the “Slave”
flip flop.

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T Flip-flops
 A T flip flop is like JK flip-flop. These are basically a
single input version of JK flip flop.

 This modified form of JK flip-flop is obtained by

connecting both inputs J and K together.

 This flip-flop has only one input along with the clock
input.

 These flip-flops are called T flip-flops because of their

ability to complement its state (i.e.) Toggle, hence the
name Toggle flip-flop.

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T Flip-flops

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Thank You
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Summary
 To use memory in a larger circuit, we need to:
 Keep the latches disabled until new values are ready to be
stored.
 Enable the latches just long enough for the update to occur.

 A clock signal is used to synchronize circuits. The cycle

time reflects how long combinational operations take.
 Flip-flops further restrict the memory writing interval, to
just the positive edge of the clock signal.
 This ensures that memory is updated only once per clock cycle.
 There are several different kinds of flip-flops, but they all serve
the same basic purpose of storing bits.

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