555 Timer IC – Working Principle, Block

Diagram, Circuit Schematics

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Here’s the internal
schematics
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555 Timer IC – PIN DIAGRAM
Represented with a block diagram it consists of 2 comparators, a flip-flop, a
voltage
divider, a discharge transistor and an output stage.
 The voltage divider
consists of
identical three 5k
which createresistors
reference two
voltages at
1/3 and 2/3 the
of
supplied
voltage, which can
range from 5 to 15V.

Next are the two comparators. A comparator is a circuit element that compares two
Analog input voltages at its positive (non-inverting) and negative (inverting) input
terminal. If the input voltage at the positive terminal is higher than the input voltage at
the negative terminal the comparator will output 1. Vice versa, if the voltage at the
negative input terminal is higher than the voltage at the positive terminal, the
comparator will output 0.
The Q-bar output of the flip-
flip goes to the output stage or
the output drivers which can
either source or sink a current
of 200mA to the load. The
output of the flip-flip is also
connected to a transistor that
connects the “Discharge” pin
to ground.
 Multivibrator
• It is the electronic circuit which is used to
implement two state devices like oscillator,
timer and flip-flop
 555 Timer – Monostable Mode
Next, let’s see how the 555 Timer works in a monostable mode.
Here’s an example circuit.
The trigger input is held High by connecting it to VCC through a
resistor. That means that the trigger comparator will output 0 to the S
input of the flip-flop. On the other hand, the Threshold pin is Low and
that makes the Threshold comparator out 0 as well. The Threshold
pin is actually Low because the Q-bar output of the flip-flop is High,
which keeps the discharge transistor active, so the voltage coming
from the source is going to ground through that transistor.
555 Timer – Monostable Multivibrator
SR flipflop Truth Table
In order to change the 555 Timer output state to High we need to press the pushbutton
on trigger pin. That will ground the trigger pin, or the input state will be 0, thus the
comparator will output 1 to the S input of the flip-flip. This will cause the Q-bar
output to go Low and the 555 Timer output High. At the same time, we can notice
that the discharge transistor is turned off, so now the capacitor C1 will start charging
through the resistor R1.
The 555 Timer will remain in this state until the voltage across the capacitor reaches 2/3
of the supplied voltage. In that case, the Threshold input voltage will be higher and the
comparator will output 1 to the R input of the flip-flip. This will bring the circuit into
the initial state. The Q-bar output will become High, which will activate the discharge
transistor as well as make the IC output Low again.
So we can notice that the amount of time the output of the 555 Timer is High, depends
on how much time the capacitor needs to charge to 2/3 of the supplied voltage, and that
depends on the values of both the capacitor C1 and the resistor R1. We can actually
calculate this time with the following formula, T=1.1*C1*R1.
Pulse Width Derivation
We know that the voltage across the capacitor C rises exponentially.
Hence the equation for the capacitor voltage VC can be written as
 Application of Monostable
multivibrator
• Linear Ramp Generator
• Frequency Divider
• Pulse width modulation
IC555 Astable Mode
 IC555 Astable Mode
Next, let’s see how the 555 Timer works in an astable mode. In this mode the IC
becomes an oscillator or also called Free Running Multivibrator. It doesn’t have a stable
state and continuously switches between High and Low without application of any
external trigger. Here’s an example circuit of the 555 Timer operating in astable mode.
Once the voltage across the capacitor reaches 1/3 of the supplied voltage, the Trigger
comparator will output 0 but at this point that won’t do any change as both R and S
inputs of the flip-flop are 0. So the voltage across the capacitor will keep rising, and
once it reaches 2/3 of the supplied voltage, the Threshold comparator will output 1
to the R input of the flip-flop. This will active the discharging transistor and now the
capacitor will start discharging through the resistor R2 and the discharging transistor. At
this moment the output of the 555 Timer is Low.
While discharging, the voltage across the capacitor starts to decline, and the Threshold
comparator right away starts to output 0, which actually doesn’t do any change as now
both R and S inputs of the flip-flop are 0. But once the voltage across the capacitor
drops to 1/3 of the supplied voltage, the Trigger comparator will output 1. This will
turn off the discharge transistor and the capacitor will start to charge again. So this
processes of charging and discharging between 2/3 and 1/3 of the supplied voltage will
keep running on its own, thus producing a square wave on the 555 Timer output.
We can calculate the time the output is High and Low using the shown formulas. The
High time depends the on the resistance of both R1 and R2, as well as the capacitance
of the capacitor. On the other hand, the Low time depends only on the resistance of R2
and the capacitance of the capacitor. If we sum the High and Low times we will get
the Period of one cycle. On the other hand, the frequency is how many times this
happens in one second, so one over the Period will give use the frequency of the
square wave output.
 Application of Astable multivibrator
• Square wave generator
• FSK Generator
• Pulse position modulator
 Comparison of the multivibrator
S.No. Monostable Astable
1 It is only one stable state There is no stable state
2 Trigger is required for the operation to Trigger is not required to change the
change the state state hence called free running
3 Two components R and C are necessary Three components RA, RB, and C are
with IC 555 to obtain the circuit necessary with IC 555 to obtain the
circuit
4 The pulse width is given The frequency is given
by W=1.1 RC sec by F=(1.44)/(RA+2RB)
Hz
5 The frequency of operation is The frequency of operation id
controlled by frequency of controlled by RA, RB and C
trigger pulses applied
6 The applications are Timer, Frequency The applications are square wave
Divider, Pulse Width Modulation etc., generator, flasher, voltage controlled
oscillator, FSK generator etc.,
What is a Schmitt Trigger?
• Schmitt trigger can be defined as it is a
regenerative comparator. It employs positive
feedback and converts sinusoidal input into a
square wave output.
• The output of Schmitt Trigger swings at upper
and lower threshold voltages, which are the
reference voltages of the input waveform.
• It is a bi-stable circuit in which the output swings
between two steady-state voltage levels (High and
Low) when the input reaches certain designed
threshold voltage levels.
 Schmitt Trigger
The circuit diagram of the Schmitt trigger using IC555 is shown below. The
following circuit can be built with basic electronic components, but IC555 is an
essential component in this circuit. Both pins of the IC such as pin-4 & pin-8 are
connected with the Vcc supply. The two pins like 2 & 6 are shorted, and the input is
mutually given to these pins with the help of a capacitor.
The mutual point of the two pins can be
supplied with an external bias voltage
(Vcc/2) using the voltage divider rule that
can be formed by two resistors namely
R1 & R2. The output keeps its values
while the input is among the two
threshold values which are called
Hysteresis. This circuit can perform like
a memory element.
The key voltage is contrasted with the The threshold values are 2/3Vcc
two threshold values using individual &1/3Vcc. The superior comparator tours
comparators. The flip-flop (FF) is at the 2/3Vcc while the minor comparator
arranged or rearranged consequently. The tours at the supply of 1/3Vcc.
output will become high or low
depending on this.
 Vcc/2

Vc
c

0
Sine wave of sufficient amplitude (> Vcc/6 = 2/3 Vcc – Vcc/2)
 PLL
• A phase-locked loop (PLL) is an electronic circuit
with a voltage or voltage-driven oscillator that
constantly adjusts to match the frequency of an input
signal. PLLs are used to generate, stabilize, modulate,
demodulate, filter or recover a signal from a "noisy"
communications channel where data has been
interrupted.
• Phase-locked loops are widely employed in radio,
telecommunications, computers and other
electronic applications.
• The reason why we use PLL is because the input
frequency is fixed which limits the application to that
certain frequency only. Thus, with the use of PLL, we
can derive different frequencies based from the input
frequency.
• A phase locked loop is basically a closed loop system
designed to lock the output frequency and phase to the
frequency and phase of an input signal. It is commonly
abbreviated as Basics of PLL.
• PLLs are available as inexpensive monolithic ICs.
• They are used in applications such as frequency
synthesis, frequency modulation/demodulation,
AM detection, tracking filters, FSK demodulator,
tone detector etc.
• The phase detector compares the input frequency fs
with the feedback frequency fo and generates an
output signal which is a function of the difference
between the phases of the two input signals.
• The output signal of the phase detector is a dc voltage.
The output of phase detector is applied to low-pass
filter to remove high frequency noise from the DC
voltage.
• The output of low pass filter without high frequency
noise is often referred to as error voltage or control
voltage for VCO. When control voltage is zero, VCO is
in free running mode and its output frequency is
called as centre frequency fo.
• The non-zero control voltage results in a shift in the
VCO frequency from its free-running frequency, fo to a
frequency f, given by
 f = fo + Kv Vc
where Kv is the voltage to frequency transfer coefficient of
VCO. the
The error or control voltage applied as an – input to the VCO, forces
the VCO to change its output frequency in the direction that reduces
the difference between the input frequency and the output frequency
of VCO.
This action, commonly known as capturing, continues till the
output frequency of VCO is same as the input signal frequency.
Once the two frequencies are same, the circuit is said to be locked.
In locked condition, phase detector generates a constant DC level
which is required to shift the output frequency of VCO from
centre frequency to the input frequency.
Once locked, PLL tracks the frequency changes of the input signal.
Thus, a PLL goes through three states. : free running, capture and
phase lock.
 Monolithic PLL
• PLL but its availability in the form of a low-cost,
self- contained monolithic circuit package.
• The PLL IC 565 is usable over the frequency
range 0.1 Hz to 500 kHz. It has highly stable
centre frequency and is able to achieve a very
linear FM detection. The output of VCO is capable
of producing TTL compatible square wave. The
dual supply is in the range of ±6V to ±12V. The IC
can also be operated from single supply in the
range 12V to 24V.
• The following figure shows the pin-out and the
internal block schematic of PLL IC LM 565
• It is a 14 pin IC, operated from a dual power
supply
+V (at pin no. 10) and –V (at pin no. 1).
Pin no 2 & 3 -> Signal input for phase detector.
Pin no 4 ->VCO output is available
Pin no 4 & 5 are shorted externally so that VCO
output is applied for phase detection. In some
applications PLL loop is broken and some circuit is
to be connected between pin no 4 and 5.
Pin no 6-> reference dc voltage is available.
Pin no 7 -> demodulated output. If input signal
between pin no 2 and 3 is FM signal then at pin no 7
we get FM demodulation output.
Pin no 8 and 9 -> external R1 and C1 for VCO
(determines free running frequency of VCO) Internal
resistance R2 and external capacitor C2 forms a
 R1 = 2 to 20Kohm

Features of IC 565:
1) Extreme stability of center frequency typically 200ppm.
2) Wide range of operating voltage ±6V to ±12V.
3) Very high linearity of demodulated output typically 0.2%
4)Centre frequency of VCO is programmable by means of resistor,
capacitor or voltage.
5) TTL compatible square wave output.
6) Highly linear triangular wave output available at pin no.9
7)Loop can be broken between pin no.4 and 5 and external circuit can be
added.
Design Equations:
1.Centre Frequency (Free running freq./ output freq./oscillator
freq.)
fo=0.3/(R1 C1 )
2. Lock range
fL=±(8fo)/V
where V=|+V|+|-V|……..(addition of two power supplies)

3. Capture range
fc=±[fL/ (2π)(3.6)(103)(C2)]1/2
 Phase Detector
• A phase detector or phase comparator is a
frequency mixer, analog multiplier or logic
circuit that generates a voltage signal which
represents the difference in phase between
two signal inputs. It is an essential element of
the phase-locked loop (PLL)
 Frequency Multiplier
• A frequency multiplier can be designed using a PLL
and a 'divided by N' counter. The frequency divider is
inserted between the VCO output (PIN 4) and phase
detector/comparator input (PIN 5) of PLL circuit.
• Therefore one input of the phase comparator is the input
signal and the other is the output of 'divided by N'
counter. when the lock is established the input
frequency fin equals the output of the counter fn.
hence fin=fn= (fout )/N ,where fout-is the vco output
frequency, therefore fout =N*fin.
• Thus when the system is in lock, the vco is actually
running at the multiple of input frequency .The desired
amount of multiplication can be obtained by selecting a
proper divide by N network, where N is an integer.
Block Diagram