Signal Integrity in HDI Digital

Electronics

by Happy Holden
PCB INDUSTRY TECHNOLOGIST

Part 3
 Outline

What's Driving Density?

Embedded Passives in PCBs

–Pwr/Gnd Capacitance
–Resistors
–Capacitors

–Cost Tradeoffs

2

Copyright ©1999-2006, Mentor Graphics.

Challenges for HDI wrt SI:
Outline
Design Challenges/Performance Tradeoffs
ƒ Signal Integrity
ƒ Electrical performance - Noise

ƒ Surface ground planes

ƒ Lumped models of vias

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

 The Design Challenge for High
Performance
Lower Costs  Reduces Size
 Reduces Layers

Signal Integrity For Advanced Packages

 Higher Density At A Lower Cost

Ease of Use For BGAs

 equired for Flip Chip  R
Components Essential for Chip Scale Packages


Materials Performance Improvements

Stackup Product Miniturization Increased Wiring Density
 

Improved Signal Integrity Lower RFI / EMI


Assembly



Improved Mechanicals
Improved Reliability
Increased Thermal Efficiency


Faster Time To Market

 Higher Layout Efficiency
 Faster Layouts

3_Signal_Integrity.ppt
HDI's ADVANTAGES
Copyright ©1999-2006, Mentor Graphics.
Circuitry

(Signal Integrity Issues)

• Characteristic Impedance
• Low Voltage Differential Signals
• Signal Loss
• Noise Sensitivity
• Power Supply Inductance
• Crosstalk
• Via Inductance

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

Four Families of SI Problems

Source: Eric Bogatin, "Signal Integrity and HDI Substrates",The Board Authority, Vol 1 no.2, June 1999
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
 Sources of Noise
Components to far apart
Very fast signal rise times
Change in trace width
Plane splits
Cutouts in Power/Ground planes
Via antipads
Insufficient plane capabilities
Excessive stubs, branched or bifurcated traces
Component lead frames
Improper impedance matching and termination networks
Coupling between signals
Varying loads and logic families
Many of these are created by the layout of the board!
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
HDI Features and SI Problems They Help Solve
Reduction of noise
Reflections
Crosstalk
Simultaneous switching
EMI/RFI reductions
Improved signal propagation and lower attenuation
Power supply coupling and reduced impedance
Signal Cross Switching EMI
HDI features quality talk Noise
Short interconnect lengths X X
Low dielectric constant X X
Small vias and small features X X
Vias in pads X
Fine lines and thin dielectric X X X
Power Coupled to Ground X X X

Support for fine-pitch components X X

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
HDI's Influence on SI

Signal Quality on One Net

Smaller pitch parts and closer spacing

Mounting component on the secondary side
Minimizing subs
Use of thin, low-dielectric constant materials
Miniaturized vias and features

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

Microstrip - Line Capacitance

Air
h FR 4 r
Ground
w
Capacitance formula

Co =
 o A
r
(pf / inch)
d
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
HDI's Influence on SI

Crosstalk Noise

Shorter interconnect lengths (smaller pitch parts,

closer spacing, mounting component on the secondary side)
Use of thin and low-dielectric constant materials

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

Crosstalk

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

Crosstalk

S
H

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

Crosstalk - Game of Ratios
-

Cm

l Co co
l
o

l
m
o

l
o Co Cm Co
Ground l
o

FR 4

FR 4

Ground

Width Gap

Keep a gap-to-width ratio of < 3:1 for < 50dB isolation

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

HDI's Influence on SI

Simultaneous switching noise

Miniaturized vias and feature geometries

Via-in-pads
Surface ground planes, close power planes
Use of thin materials

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

 Return Path - Ideal
Ideal - continuous and uniform

DC

AC
DC

DC - Path of least resistance - (blue print)

AC - Path of least inductance - (red print)
l0 l0 l0
Transmission Line
AC Model C0 C0 C0
Image Plane
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
 NON-Ideal - Ground Loop

Return Path - Discontinuous

BGA GND antipads

loop

Ground Break

Ground Ground

Ground loop
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
Ground Planes for Thru-holes

cut-out area = 8.46 square inch

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
Surface Ground Planes for HDI

cut-out area = 6.63 square inch, 21.6% less

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
Surface Ground Planes for HDI

cut-out area = 6.35 square inch, 24.9% less

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
Via-In-Pad Area Reduction
before after

40% reduction in area,

33% reduction in layers

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

Via-In-Pad Area Reduction
before after

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

HDI's Influence on SI

EMI radiation / susceptibility

Ground planes on surface

Miniaturized vias and features
Support for fine-pitch component
Closer spacing to ground planes
Improved signal return path

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

 Comparison of Electrical
Performance
mechanically drilled via (8 layers)

HDIS blind via

0.05 mm
(.002")
1.6 mm .015 nH
(.064")

.04 pF .04 pF

.132 nH .132 nH .132 nH .132 nH

.07 pF .054 pF .053 pF .054 pF .054 pF .07 pF

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
Pad Inductance

Earlier designs

96 designs

98 designs

early HDI

current HDI

TIME future HDI

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

Inductance of Decoupling
Capacitor

Componen
t
Groun
Conventional d

Power

Capacitor

Componen
t
Better Groun
d
Power

Capacitor

Component/
Ground
Best Power

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
 Switching Noise - Bypassing

CONVENTIONAL MICRO VIA IN PAD

.1UF
.O1UF .1UF
V+
PWR
PWR
GND GND

GND
GND
l l l l
l = 3nh l =0.3nh
1 2
1 2
1
V+ 1

C1 .01 C2
l = 3nh
2
.1 C = l = 3nh
2
f *c1
1

C2=.1 f
C2
* C =600pf/sq.in
1
* patch capacitor C2=.1f

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

 Advantages Planes on Outerlayers
shielding for RFI (radio frequency interference) because of stripline structure
controlled impedance on all signal layers possible
you can put 1 signal layer or 2 perpendicular
signal layers between 2 planes
decreased loop area
improved RFI performance
VIP, planes on Outerlayer:
pads on Outerlayer
conventional TH (pads and lines on OL):
component

pads on Outerlayer
ground plane
loop area is size of component, pad and blind via
component

power plane

loop area is size of component

breakout & stackup

ground plane

power plane

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

Ground Loops - Thru-vias Vs. Microvias

Conventional inner layer ground

Micro-via, outer layer ground/pads

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
 HDI Power and Ground

4
0
COPYRIGHT HHolden 2006 Copyright ©1999-2006, Mentor Graphics.
 Power Supply Impedance

4
1
COPYRIGHT HHolden 2006 Copyright ©1999-2006, Mentor Graphics.
 Via Hole Inductance

4
2
COPYRIGHT HHolden 2006 Copyright ©1999-2006, Mentor Graphics.
 Plane Capacitance and Inductance

4
3
COPYRIGHT HHolden 2006 Copyright ©1999-2006, Mentor Graphics.
Various PWRs Closer to the Surface
Single PWR Plane

Split PWR Plane

SMT/GND
PWR
SIG L-1
L-2

Mesh PWR Plane

tied to N-1 Mesh
PWR Plane
L-(N-1)
L-(N)

4
4
Copyright ©1999-2006, Mentor Graphics.
 Power Supply Coupling

L-1

L-2

L-(N-1)

Mesh PWR Plane Conventional inner layer ground

tied to N-1 Mesh
L-(N)
PWR Plane

Micro-via, outer layer ground/pads

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
PC Board Properties-

4
6
Copyright ©1999-2006, Mentor Graphics.
END OF PART 3I
4
7
Copyright ©1999-2006, Mentor Graphics.
THANK-YOU
 Wave Length Analysis
Co
= --------

f ef 
lamda = wave length
10 100%
C0(speed of light) = 3*10 cm/sec
90
f

%
reff = 3.4(FR-4 microstrio in air)
 C o
= --------
10 10f ref 10%

f 0%
LENGTHshort must be less
d

than 20% of d*30.4 tim
Rise tim
Fall
interconnect
in/nsec/r length = 2.92 cm=1.15 inch
e e

f (frequency) = 0.37 d 
 3*1010
cm/s
= ------------------- 
ex: if d = 1 ns, f = 370 Mhz
10 10*(370x106*3.4 The openings in your PC board should be less
than 1/10 wavelength in order to contain or not
= 2.38cm=0.94 inch be susceptable to a specific wave length.
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
 Transmission Structures - r, Z0,d

Ground
FR 4
Air

FR 4 r h FR 4
Ground
Ground
w

Microstrip Stripline
r r
eff  Medium: Air and FR 4)
eff =  r = 4.5 (Homogeneous Medium)
Zo = loCo Zo =  loCo l o and Co have the exactly the
same sensitivity to trace dimensions.

Zo h, 1/w, 1/ r eff Zo h, 1/w, 1/ r eff

d=   r eff , Slightly dependent d=   r eff , = loCo, Independent of width
vo on width (second order effect) vo
3_Signal_Integrity.ppt Superior EMI Solution-Faraday cage
Copyright ©1999-2006, Mentor Graphics.
Switching Noise (ground bounce)
l v

l v

dt
l
V= di
Lead Frame
Die

Power trace
145 micron- Micro-via
Power-via

Keep all power and ground breakouts short (5-10 mils) and power traces wide (12-
20 mils).
3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.
Switching Noise - Packaging
Alternatives
Die Attach Lead Frame Powertrace Via Package solution
Bond QfP 15-20nh Standard 5-10nh Drilled nh Bond/ QfP/ Standard breakout/
1-2nh
Wire breakout Drilled 25-36nh

Solder SOIC 6-10nh Outer .12nh Micro nh Bump/ CSP/ outer
.7-1nh
Bump layer ground/ 3.82-6.62nh
BGA 6-10nh Ground Micro-via

CSP 3-5nh

Example- Clock Distribution:

8 clock drivers in a package simultaneously switching between
8 and 64 ma in 1.5 ns.
l
1. Bond/qfp/standard breakout/drilled via V= di/dt =36 nh (56ma/1.5ns)= 1.3 volts
l
2. Bump/csp/outer ground/Micro-via V= di/dt= 3.82nh (56ma/1.5ns)=143 mv

3_Signal_Integrity.ppt Copyright ©1999-2006, Mentor Graphics.

Transmission Structures
Definitions
Dielectric: an electrical
the abilityinsulator
of a dielectric to store or hold
Permittivity: electrons

Relative permittivity: the ratio of an capacitor made from

an insulator between the plates compared to one built with a
vacuum.  = permittivity
o = Zero (a vacuum)
o = permittivity of a vacuum
r = relative
r = Permittivity, relative to a vacuum
Various Er: vacuum=1.000, air=1.0007, teflon=2.2, polystyrene=2.5,
mylar=3.0, epoxy=3.2, paper,paraffin=4.0, glass=6.0, tantalum oxide=25,
ceramic=10, water=75, ceramic=100-10k
Impedance: is the combined inductive reactance and
capacitive reactance
Transmission Structures


 r
 d= --------
Vo

Medium r d (ns/ft) Note

Air 1.0 1.017 speed of light
PTFE 2.2 1.51 coax
Cyanate Ester 3.6 1.95 servers
PPE 3.4 1.90 networking
Polyimide 2.8 1.7 MCM-stripline
FR4-Air 3.4 1.87 microstrip
FR4 4.4 2.16 stripline
Ceramic 9-16 3.05-3.9 MCM-stripline
Substrate Materials
Performance Comparison
Material Supplier(s) Tg Dissipation Water Material
(DSC) Dielectric Factor CTE-Z CTE-X&Y Absorption Cost
(deg C) Constant (@ 1 MHz) (ppm/C) (ppm/C) (%) Adder
Tetrafunctional Polyclad (FR-226) 140 4.5 0.019 60 15 0.09 1
Epoxy (FR-4) Nelco (N4000-2)
NanYa CCL
Multifunctional Polyclad (FR-370) 180 4.4 0.012 60 15 0.09 1.2
Epoxy (FR-4) Nelco (N4000-6)
NanYa CCL-180
Bismaleimide Allied Signal 180 4.1 0.013 50 13 0.19 1.5
Triazine (BT) G200
GETEK General Electric 180 3.6-4.2 0.013 50 13 0.12 1.4
(E glass)
Tetra II Plus Polyclad (FR-370G) 180 3.9 0.01 45 14 0.09 1.3

DrIclad IBM 170 4.1 0.011 60 17 0.17 1.2

SYCAR resin Polyclad (FR-511) 190 3.6 0.005 45 14 0.04 2.6

(E-glass) (DMA)
Thermount Nelco (N7000-2T) 220 4.1 0.022 85 8.5 0.4 3.5
Arlon 220 3.9 0.014 80 8.0 .35 4.5
Polyimide Blend Nelco (N7000-2) 250 4.3 0.014 70 13 .0.3 2.5
(E glass)
Cyanate Ester(E- Nelco (N8000) 250 3.8 0.005 55 12 0.45 3.5
glass)
Cyanate Ester (S- Nelco (N8000S) 250 3.6 0.005 50 9 0.45 6
glass) NanYa CCL (LDC)
Polyimide (E- Nelco (N7000-1) & 260 4.3 0.013 70 13 0.35 3
glass) Arlon
PPE (SI-glass) Nelco (6000SI) 280 3.6 .004 60 14 0.09 1