ĐẠI HỌC QUỐC GIA TP.

HỒ CHÍ MINH
ĐẠI HỌC BÁCH KHOA
NGÀNH KỸ THUẬT ĐIỆN TỬ

CHƯƠNG 2
MÔ HÌNH HÓA, HOẠT ĐỘNG,
TÍNH CHẤT CỦA CMOS
Hoàng Trang, Nguyen Minh Hieu
Bộ môn Kỹ Thuật Điện Tử
[email protected]

1
TP.Hồ Chí Minh 01/ 2014
 Outline

0. Introduction.
1. Transistor Review.
2. MOS Characteristic.
3. Non-Ideal Effect.
4. MOS Device Model.
5. MOS Behaviour Model.
6. CMOS Planar Process.

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 Outline

0. Introduction.
1. Transistor Review.
2. MOS Characteristic.
3. Non-Ideal Effect.
4. MOS Device Model.
5. MOS Behaviour Model.
6. CMOS Planar Process.

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 Introduction
Classification of Silicon Technology
Silicon IC Technology

BJT BiMOS MOS

Junction Dielectric Oxide CMOS PMOS NMOS

Germaninium - Silicon Aluminium Aluminium Aluminium Silicon

Silicon
Silicon

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 Introduction
Why CMOS Technology

CATEGORY BJT CMOS

Transconductance gm (Analog) 4mS @ 100uA 0.4mS (W=10L) @ 100uA

Small signal output resistance Larger Smaller for short channel
Cutoff Frequency(fT) 100 GHz 50 GHz (0.25μm)
Noise (1/f) Good Poor
Switch Implementation (Logic) Poor Good
Power Dissipation Moderate to High Low
Technology Improvement Slower Faster

Bipolar vs MOS Transistor

Since 1987 : Introduction of BiCMOS to keep the advantages of both
Bipolar and CMOS technologies

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 Introduction
Since middle 1980’s : CMOS becomes the predominant technology
Since 1997: BiCMOS declines (Intel switched BiCMOS Pentium to CMOS)

Technology Market Trends

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 Outline

0. Introduction.
1. Transistor Review.
2. MOS Device Model.
3. CMOS Characteristic.
4. CMOS Behavior Model.
5. Second-Order Effect.
6. Long Chanel versus Short Chanel.

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 Transistor Review

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 Transistor Review
Vout
AV    KRL
Vin

A voltage-dependent current source can act as an amplifier.

If KRL is greater than 1, then the signal is amplified.

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 Transistor Review

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 Transistor Review

VBE
I C  I S exp
VT
1 V
IB  I S exp BE
 VT
 1 V
IE  I S exp BE
 VT


 1

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 Transistor Review

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 Transistor Review

d V 
gm   I S exp BE 
dVBE
 VT 
1 V
gm  I S exp BE
VT VT
IC
gm 
VT
Transconductance, gm shows a measure of how well the transistor converts voltage to current.
It will later be shown that gm is one of the most important parameters in circuit design.
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 Transistor Review
Ebers-Moll model

•Substrate •E •B •E

•p•+ •p•+ •n•+ •p•+

•n

•Si •p

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 Outline

0. Introduction.
1. Transistor Review.
2. MOS Characteristics.
3. CMOS Characteristic.
4. CMOS Behavior Model.
5. Second-Order Effect.
6. Long Chanel versus Short Chanel.

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 MOS Transistors
MOS Capacitor

Vg
gate
metal
SiO2

Si body

MOS capacitor
Structure

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 MOS Transistors
MOS Structure and Symbol

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 MOS Transistors
MOS Structure and Symbol

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 MOS Transistors

VDD VDD VDD

PMOS NMOS CMOS

From MOS To CMOS …

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 MOS Transistors
MOS Structure and Symbol

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 MOS Transistors
MOS Structure and Symbol

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 MOS Characteristics
How does the device turn on and off?
What is the drain-source current
when the device is on?

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 MOS Characteristic
Threshold Voltage

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 MOS Characteristic
Threshold Voltage

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 MOS Characteristic
Threshold Voltage

The MOS characteristics are

measured by varying VG while
keeping VD constant, and varying
VD while keeping VG constant.

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 MOS Characteristic
Drain Current

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 MOS Characteristic
Drain Current

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 MOS Characteristic
Drain Current

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 MOS Characteristic
Drain Current

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 MOS Characteristic
Drain Current

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 MOS Characteristic
Drain Current (Pinch-Off)

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 MOS Characteristic
Some Effects

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 MOS Characteristic
Sumary

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 MOS Characteristic
Sumary

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 MOS Characteristic
Sumary

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 MOS Characteristic
Sumary

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 MOS Characteristic
Transconductance

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 MOS Characteristic
Transconductance

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 MOS Characteristic
Transconductance

W W 2I D
g m   nCox VGS  VTH  g m  2  nCox ID gm 
L L VGS  VTH
Transconductance is a measure of how strong the drain current
changes when the gate voltage changes.

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 Outline

0. Introduction.
1. Transistor Review.
2. MOS Characteristic.
3. Non-Ideal Effect.
4. CMOS Behavior Model.
5. Second-Order Effect.
6. Long Chanel versus Short Chanel.

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 Second-Order Effect
Body Effect

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 Second-Order Effect
Body Effect

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 Second-Order Effect
Body Effect

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 Second-Order Effect
Chanel Length Modulation

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 Second-Order Effect
Chanel Length Modulation

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 Second-Order Effect
Chanel Length Modulation

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 Leakage Effect
Sub Threshold Leakage

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 Leakage Effect
Source/Drain Leakage

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 Leakage Effect
Gate Leakage

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 Leakage Effect
Drain-Induced Barrier Lowering (DIBL)

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 Leakage Effect
Drain-Induced Barrier Lowering (DIBL)

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 Second-Order Effect
Gate-Induced Drain Leakage (GIDL)

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 Leakage Effect
Drain-Induced Barrier Lowering (DIBL)

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 Short Chanel Effect
Velocity Saturation

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 Short Chanel Effect
Long Chanel versus Short Chanel

Short-channel NMOSFET:
• IDsat is proportional to VGS-VTn rather than (VGS-VTn)2
• VDsat is lower than for long-channel MOSFET
• Channel-length modulation is apparent
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 Short Chanel Effect
Short Chanel Effect (SCE)
“VT roll-off”

• |VT| decreases with L

– Effect is exacerbated by
high values of |VDS|

• This effect is undesirable (i.e. we want to minimize it!)

because circuit designers would like VT to be invariant
with transistor dimensions and bias condition
Faculty of Electronics Engineering Spring 2014 Analog Integrated Circuit Design Course
 Outline

0. Introduction.
1. Transistor Review.
2. MOS Characteristic.
3. Non-Ideal Effect.
4. MOS Device Model.
5. Second-Order Effect.
6. Long Chanel versus Short Chanel.

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 MOS Device Model
Device Capacitance

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 MOS Device Model
Device Capacitance

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 MOS Device Model
Device Capacitance

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 MOS Device Model
Device Capacitance

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 MOS Device Model
Device Capacitance

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 MOS Device Model
Device Capacitance

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 MOS Device Model
Sumary

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 Outline

0. Introduction.
1. Transistor Review.
2. CMOS Characteristic.
3. Non-Ideal Effect.
4. MOS Devices Model.
5. MOS Behaviour Model.
6. Long Chanel versus Short Chanel.

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 MOS Behaviour Model
Small Signal Model

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 MOS Behaviour Model
Small Signal Model

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 MOS Behaviour Model
Small Signal Model

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 MOS Behaviour Model
Small Signal Model

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 MOS Behaviour Model
Small Signal Model

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 MOS Behaviour Model
Ký Tên Mô tả [2] Giá trị Đơn vị
hiệu
VTH0 VT0 Ngưỡng áp phân cực 0.489 Volts (V)
γ. Gamma Thông số hiệu ứng thân 667.E-3 V1/2
2|Vfp| Phi Điện th mặt và cực Bulk 450.0E-3 V
ID Ids Dòng phân cực Đo A

VDSsat Vdsat Ngưỡng điện áp bão hòa 0.0415 V

KP KP Thông số hỗ dẫn 390.0 uA/V2

SPICE Model C’ox Tụ điện cực cổng đơn vị 4.1E-9 fF/um2

Cox Tụ điện cực cổng 8.58E-3 fF/um2

λ Lamda Thông số điều chế L kênh 0.5 V-1

CGS Cgs0 Tụ ký sinh cực G và S 3.65e-16 F

CGD Cgd0 Tụ ký sinh cực G và D 3.65e-16 F

Ron Ron Điện trở On Đo ohm

Gm gm Hỗ dẫn của CMOS Đo mho

Gmb gmb Hổ dẫn Body effect Đo mho

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 Outline

0. Introduction.
1. Transistor Review.
2. MOS Device Model.
3. CMOS Characteristic.
4. CMOS Behavior Model.
5. Second-Order Effect.
6. CMOS Planar Process.

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 CMOS Planar Process
•Silicon oxidation •SiO2 etching
S iO 2

Si p Si p

•SiO2 masking •Impurities n diffusion

P h o to resist
S iO 2 S iO 2
nn n
Si p Si p

V isib le or U V lig h t
M a sk

P h o to re sist
S iO 2

Si p •Impurities p+ diffusion
P h o tore sist p+ p+
S iO 2
S iO 2 n n
Si p
Si p

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 CMOS Planar Process
n W e ll n+ n+ p+ p+
n
Si p Si p
T hin S i O 2

n p+
n+ n+ p+
Si p n
Si p
P o ly silico n

n p+
n+ n+ p+
Si p n
Si p

T ran sisto r N M O S T ran sisto r P M O S

n+ n+ p+ p+
n
Si p

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 CMOS Planar Process
Transistor NMOS and PMOS

S G D D G S W ell S u b strate

n+ n+ p+ p+ n+
n
Si p

T ra n sisto r N M O S T ra n sisto r P M O S
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 CMOS Planar Process

•Diode p+-well

•Substrate •C •A

•p•+ •n•+ •p•+ •n •p•+ •p•+

•p
•Si

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 CMOS Planar Process
•Capacitor p+-well
•R •C
•Substrate •P •N •N
•P
•p•+ •n•+ •p•+
•n
•p
•Si •C•S

•Substrate

n n n •Bottom capacitor
Cb 0
Cb  1/ 2
 U inv 
1  U 
200 um  b0 

•Sidewall capacitor
p+ p+
Csw0
Csw  1/ 3
 U inv 
40 pF
1  U 
 b0 

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 CMOS Planar Process
•Capacitor n+-Poly
•Substrate •P •Poly

•p•+ •n•+
•n
•Si •p

•R •C
•P(n+) •Poly

•C
•S

•Substrate

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 CMOS Planar Process
•Capacitor Poly-Poly •Capacitor Metal-Metal (MiM)

•P•o••ly•1 •P•o••ly•2 •Metal1 •Metal2

•S•i •p •p
•S•i

•Cmetal-metal: 1fF/µm2
•Cpoly-poly: 1fF/µm2

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 CMOS Planar Process

•Diffused Resistors

•Current direction if Well connected to R A

•Substrate •RA •RB •Well •RA •RB

•p•+ •n•+ •n •n•+ •n•+ •p•+

•n
•p
•Si

•R□nwell: 500 Ω/sq •R□p+: 7 to 60 Ω/sq

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 CMOS Planar Process

•Poly Resistors

•R •R

•Si •p

•R□poly: 7 Ω/sq

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 CMOS Planar Process
•Doping p+

•Cut•A-A'

•Poly p •poly n
•SiO2
•p+ •n+
•n
•Si •p

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 CMOS Planar Process
•Transistors MOS parasites

•Metal
•S •G •D •--------- •S • G •D

•p•+ •p+ •p+ •p+

•n
•Si •p

•Metal •S •G •D
•S •G •D •---------

•p•+ •p+ •n+ •p+ •p+

•n
•Si •p

•channel stopper

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 HomeWork

From Razavi Book

1. Problem 2.5 (c), (e)
2. Problem 2.6 (b), (e)
3. Problem 2.7 (b), (c)
4. Problem 2.8 (c)
5. Problem 2.9 (b), (c)
6. Problem 2.10 (a)
7. Problem 2.11 (a), (b)
8. Problem 2.26

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 References

[1] Phillip E.Allen, Douglas R.Holberg, “CMOS Analog Circuit Design”,

2nd Edition, Oxford Univeristy Press, 2002.

[2] Behad Razavi. "Design of Analog CMOS Integrated Circuits",

International Edition, Electrical and Computer Engineering Series,
McGraw-Hill, 2001

[3] R. Jacob Baker. "CMOS Circuit Design, Layout, and Simulation", 3rd
Edition, IEEE Press Series on Microelectronic Systems, A Join Wiley &
Son, 2010 .

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