HARDWARE DESCRIPTIVE

LANGUAGE: VHDL
A. Jawahar
SSN College of Engineering
 Session Objectives

• To learn about the VHDL Design units

• To choose the appropriate model to simulate the given
circuit
 Session Outcomes

At the end of the session, students will be able to

•Understand the five design units in VHDL
•Choose the appropriate model for the given problem
•Know the different key words used and its syntax in the
VHDL
 VHDL Design Units

VHDL provides five different types of primary constructs called

design Units.
 Entity Declaration
 Architecture Body
 Configuration Declaration
 Package Declaration
 Package Body
 Entity Declaration

 Describes the external view of the entity

 Specifies the name of the entity being modeled and lists the set of
interface ports.

 Ports are signals through which the entity communicates with the
other models in its external environment.

 Specifies the declarations and statements that are part of the design.

 May be shared by many design architectures.

 Entity Declaration

entity entity_name is
port ( [signal] identifier
{, identifier}: [mode] signal_type
{; [signal] identifier
{, identifier}: [mode] signal_type});
end [entity] [entity_name];

entity HALF_ADDER is
port (A,B: in BIT; SUM, CARRY: out BIT);
end HALF_ADDER;
 Architecture body & Declaration Styles

 Internal details of an entity are specified

 Structural Modeling
 As a set of interconnected components to represent structure.
 Data Flow Modeling
 As as set of concurrent assignments statements to represent
data flow.
 Behavioral Modeling
 As a set of sequential assignment statements to represent
behavior.
 Architecture Declaration

architecture architecture_name of entity_name is

type_declaration | signal_declaration
| constant_declaration | component_declaration
| alias_declaration | attribute_specification
| subprogram_body
begin
{process_statement
| concurrent_signal_assignment
| component_instantiation_statement
| generate_statement}
end [architecture] [architecture_name];
 Structural Modeling

 An entity is described as a set of interconnected components

 Architecture body composed of two parts
 Declarative part
 Specify the interface of the components
 Statement part
 Instantiate the declared components
Entity Construct
Entity Examples
VHDL Keywords
Example - Half Adder
 Structural style of Modeling

architecture HA_STRUCTURE of HALF_ADDER is

component XOR2
port (X,Y:in BIT;Z:out BIT);
end component;
component AND2
port (L,M:in BIT;N:out BIT);
end component;
begin
X1:XOR2 port map (A,B,SUM);
X2:AND2 port map (A,B,CARRY);
end HA_STRUCTURE;
 Component Declaration
 Appears in declaration part of an architecture body.
 Declares the name and interface of a component in a structural
description.
 Interface specifies the mode and the type of ports.

component component name [is]

[port (list of interface ports);]
end component [component name];
 component-name
 may or may not refer to the name of an entity already existing in a library
 if it does not exists, it must be explicitly bound to an entity.
 list-of-interface-ports
 specify the name, mode & type for each port (similar in entity
declaration).
 Component Instantiation
 Represents an entity/architecture pair.
 Instantiations of components in architectures is a method to define
hierarchy because architectures of components can have within
them other components.

 Defines sub-component of the entity in which it appears.

 Associates the signals in the entity with the ports of that sub-
component.

 Associates values with generics of that sub-component.

 Is equivalent to plugging a hardware component into a board and

making the electrical connections between the pins of the component
and the signals of the circuit board.
component-label: component-name
[port map (association_list)];

 component-label: name of the instance (legal identifier).

 component-name: must be the name of the component declared
earlier using a component declaration.
 association-list: associates signals in the entity, called actuals, with
the ports of a component, called formals.
 actuals
 may be a signal, an expression for an input port, the keyword
open to indicate a port that is not connected.
 formals
 two ways to perform association of formals with actuals:
positional association and named association.
 Positional Association

 Association list of the form:

 actual1, actual2, actual3, …, actualn
 Each actual in the component instantiation is mapped by position
with each port in the component declaration.

---- signal declaration

signal s1, s2, s3;
---- component declaration
component nand2
port (a, b: in std_logic; z: out std_logic);
end component;
---- component instantiation
n1: nand2 port map (s1, s2, s3);
 Named Association
 Association list of the form:
 formal1 =>actual1, …, formaln => actualn
 Each actual in the component instantiation is mapped by name with
each port in the component declaration.

---- signal declaration

signal s1, s2, s3;
---- component declaration
component nand2
port (a, b: in std_logic; z: out std_logic);
end component;
---- component instantiation
n1: nand2 port map (a => s1, b => s2, z => s3);
 Association Rules
 The types of the formal and actual being associated must be the
same.
 The modes of the ports must conform to the rule that if the formal is
readable, so must the actual be, and if the formal is writable, so
must the actual be.
 Since a locally declared signal is considered to be both readable
and writable, such a signal may be associated with a formal of any
mode.
 If an actual is a port of mode in, it may not be associated with a
formal of mode out or inout.
 If an actual is a port of mode out, it may not be associated with
a formal of mode in or inout.
 If an actual is a port of mode inout, it may be associated with a
formal of mode in, out or inout.
Concurrent signal assignments (CSA)
Full Adder
entity fulladd is entity entity_name is
port (a, b, c: in bit; sum, cout: out bit); port ( [signal] identifier
end fulladd; {, identifier}: [mode] signal_type
architecture fulladd_str of fulladd is
component XOR {; [signal] identifier
port (k, l: in bit; m: out bit); {,identifier}:[mode]signal_type});
end component; end [entity] [entity_name];
component AND2 architecture architecture_name of entity_name is
port (n, o : in bit; p: out bit); type_declaration | signal_declaration
end component; | constant_declaration | component_declara
component OR3 || subprogram_body
port (t,q, r : in bit; s: out bit); begin
end component; {process_statement
signal s1, c1, c2, c3: bit; | concurrent_signal_assignment
begin | component_instantiation_statement
| generate_statement}
X1: XOR port map (a, b, s1);
end [architecture] [architecture_name];
X2: XOR port map (s1, c, sum);
A1: AND2 port map (a, b, c1);
A2: AND2 port map (a, c, c2);
A3: AND2 port map ( b, c, c3);
O1: OR3 port map (c1, c2, c3, cout);
end fulladd_str;
 Defining Structure in VHDL

Full Adder circuit

Interface description
of the half-adder and
or gate
Full adder example
Decoder 2-to-4
entity decoder_2_to_4 is
port (a, b, en: in bit; data: out bit_vector (0 to 3);
end decoder_2_to_4;
architecture decoder_str of decoder_2_to_4 is
component NOT
port (d: in bit; e: out bit);
end component;
component NAND3
port (p, q, r: in bit; s: out bit);
end component;
signal a_bar, b_bar: bit;
begin
I0: NOT port map (a, a_bar);
I0: NOT port map (b, b_bar);
N0: NAND3 port map (en, a_bar, b_bar, data(0));
N1: NAND3 port map (en, a_bar, b, data(1));
N2: NAND3 port map (en, a, b_bar, data(2));
N3: NAND3 port map (en, a, b, data(3));
end decoder_str;
 Decoder
entity decoder is
port (a, b, en: in bit; z: out bit_vector( 0 to 3));
end decoder;
architecture deco_behave of decoder is
begin
process (a, b, en)
variable abar, bbar: bit;
begin
abar := not a; bbar := not b;
if en = ‘1’ then
z(0) <= not (abar and bbar);
z(1) <= not (abar and b);
z(2) <= not (a and bbar);
z(3) <= not (a and b);
else
z <= “1111”;
end if;
end process;
end deco_behave;
 open

 If a port in a component instantiation is not connected to any signal,

the key word open can be used to signify that the port is not
connected.

---- signal declaration

signal s1, s2, s3;
---- component declaration
component nand2
port (a, b: in std_logic; z: out std_logic);
end component;
---- component instantiation
n1: nand2 port map (s1, open, s3);
 Summary

 Logic design review

 Write VHDL models (five design units)
 Structural Modeling using VHDL
 Assessment Questions
• What is the function of entity declaration and write its
syntax? Write the entity declaration for Half Adder.
• What are the three styles or models a digital circuit can be
represented in VHDL?
• What is the difference between named association and
positional association?
• Write the association rules.
• Write a program for full adder / decoder / multiplexer /
comparator using VHDL structural modeling.
 Reference Material

• Kenneth L. Short, VHDL for Engineers, Prentice Hall, 2009.

• Morris Mano M and Michael D. Ciletti, Digital Design,
Pearson, Fifth Edition, 2015.
• Salivahanan S and Arivazhagan S, Digital Circuits and
Design, Oxford University Press, Fifth Edition, 2017.