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Structures For Discrete Time Systems

This document discusses different implementations and representations of discrete-time linear time-invariant (LTI) systems. It describes how LTI systems can be characterized by their transfer function H(z) and the computations needed to realize them. The key implementations are direct form, canonical form, cascade form, and parallel form. Block diagram and signal flow graph representations are also introduced and an example system is illustrated in both forms. It requires 2 adders, 3 multipliers, and 2 delay elements to implement the example system. Infinite impulse response (IIR) filters, which have at least one pole in their transfer function H(z), are also briefly discussed.

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Shubham Bhalerao
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40 views

Structures For Discrete Time Systems

This document discusses different implementations and representations of discrete-time linear time-invariant (LTI) systems. It describes how LTI systems can be characterized by their transfer function H(z) and the computations needed to realize them. The key implementations are direct form, canonical form, cascade form, and parallel form. Block diagram and signal flow graph representations are also introduced and an example system is illustrated in both forms. It requires 2 adders, 3 multipliers, and 2 delay elements to implement the example system. Infinite impulse response (IIR) filters, which have at least one pole in their transfer function H(z), are also briefly discussed.

Uploaded by

Shubham Bhalerao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Structures for Discrete Time

Systems
Realization of digital filters (IIR & FIR)

When causality is assumed, a LTI filter can be uniquely characterized by its transfer
function H(z):

where x[n] and y[n] are the system input and output
Assuming a0 ≠ 0 , the output is: • How many storage elements are
needed?
• How many multipliers are needed?
• How many adders are needed?
Assigning ak/a0 =ak and bk/a0=bk or a0=1, then Computations of y[n] can be arranged in
different ways to give the same difference
equation, which leads to different
structures for realization of discrete-time
LTI systems
To compute y[n], we need 4 basic forms of implementations, namely,
 Delay elements or storage direct form, canonic form, cascade form
and parallel form will be described
 Multipliers An implementation can be represented
using either a block diagram or a signal
 Adders (subtraction is considered as addition)
flow graph
Block Diagram Representation
• Although an adder can generally deal with more than two
sequences, here we consider two signals in order to align
with practical implementation in microprocessors.
• When |α| > 1, it corresponds to signal amplification while
the signal is attenuated for |α| < 1. Note that a multiplier
usually has the highest implementation or computational
cost and thus it is desired to reduce the number of
multipliers in different systems, if possible.
• The transfer function z-1 corresponds to a unit delay. It can be
implemented by providing a storage register for each unit
delay in digital implementation. If the required number of
samples of delay is D > 1, then the corresponding system
function is z-D.
Signal Flow Graph Representation
• Its basic elements are branches with directions, and nodes.
That is, a signal flow graph is a set of directed branches that
connect at nodes.
• Signal at a node of a flow graph is equal to the sum of the
signals from all branches connecting to the node.
• Signal out of a branch is equal to the branch gain times the
signal into the branch.
• Branch gain can refer to a scalar or a transfer function of z-1
corresponding to multiplication or unit delay operation,
respectively.
• When the branch gain is unity, it is left unlabeled.
• A signal flow graph provides an alternative but equivalent
graphical representation to a block diagram structure
Draw the block diagram and signal flow graph representations
of a LTI system whose input x[n] and output y[n] satisfy the
following difference equation:

Illustration of block diagram


Illustration of signal flow graph

• 2 adders,
• 3 multipliers and
• 2 delay elements are required to implement the
system.
Structures for Infinite Impulse Response (IIR) Filter

When there is at least one pole in H(z), it corresponds to an IIR filter.


The corresponding transfer function is thus:

That is, IIR filter is the general form of any discrete-time LTI
system.

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