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VHDL Basics

This document provides an introduction to VHDL (VHSIC Hardware Description Language). It discusses what HDL stands for, why VHDL is used, basic VHDL notation, how to write VHDL code. It also covers VHDL modeling styles including data flow, structural, and behavioral models. Examples are given showing how to implement a half adder circuit using each of these three styles.

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Priya Priya
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29 views

VHDL Basics

This document provides an introduction to VHDL (VHSIC Hardware Description Language). It discusses what HDL stands for, why VHDL is used, basic VHDL notation, how to write VHDL code. It also covers VHDL modeling styles including data flow, structural, and behavioral models. Examples are given showing how to implement a half adder circuit using each of these three styles.

Uploaded by

Priya Priya
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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VHDL BASICS

BY
SANTOSH KUMAR PADHI
RESEARCH SCHOLAR
ECE DEPARTMENT
What does HDL stand for?
Why use an HDL ?
Introduction To VHDL
Introduction To VHDL(contd…)
Introduction To VHDL(contd…)
VHDL Notation 1
VHDL Notation 2
How do we write code?
Basic Form of VHDL Code
Standard Libraries
Entity Declaration
Port Declaration
Architecture Declaration
Modeling Styles
VHDL Hierarchy
Sequential Vs Concurrent Statements
Data Flow Model
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_adder_df is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end half_adder_df;

architecture Behavioral of half_adder_df is

begin

s <= a xor b;
c <= a and b;

end Behavioral;
Structural Model
library ieee; component and_gate -- and
use ieee.std_logic_1164.all; component declaration
port (i1, i2: in std_logic;
entity half_adder is -- Entity declaration for o1: out std_logic);
end component;
half adder
port (a, b: in std_logic; begin
sum, carry_out: out std_logic); u1: xor_gate port map (i1 => a, i2
end half_adder; => b, o1 => sum);
architecture structure of half_adder is u2: and_gate port map (i1 => a, i2
-- Architecture body for half adder => b, o1 => carry_out);
-- We can also use Positional
component xor_gate -- xor component Association
declaration -- => u1: xor_gate port map (a, b,
port (i1, i2: in std_logic; sum);
o1: out std_logic); -- => u2: and_gate port map (a, b,
end component; carry_out);
end structure;
Behavioral Modeling
library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port (a, b: in std_logic;
sum, carry_out: out std_logic);
end half_adder;

architecture behavior of half_adder is


begin
ha: process (a, b)
begin
if a = ‘1’ then
sum <= not b;
carry_out <= b;
else
sum <= b;
carry_out <= ‘0’;
end if;
end process ha;
end behavior;
Thank You

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