Scribd
Upload
314 views

VLSI-PPT-Module-3-Delays and Subsystems

This document is a module outline for a course on VLSI Design. It discusses the following topics: 1. Delay and combinational circuit design, including delay models, logical effort of paths, and introduction to combinational circuits. 2. Combinational circuit design families like static CMOS, ratioed circuits, cascode voltage switch logic, and pass transistor circuits. 3. The module aims to help students understand MOS transistor theory, design basic gates, combinational, sequential and dynamic logic circuits, memory elements, and testing issues in VLSI design.

Uploaded by

Chandra Shekar Medar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
314 views

VLSI-PPT-Module-3-Delays and Subsystems

This document is a module outline for a course on VLSI Design. It discusses the following topics: 1. Delay and combinational circuit design, including delay models, logical effort of paths, and introduction to combinational circuits. 2. Combinational circuit design families like static CMOS, ratioed circuits, cascode voltage switch logic, and pass transistor circuits. 3. The module aims to help students understand MOS transistor theory, design basic gates, combinational, sequential and dynamic logic circuits, memory elements, and testing issues in VLSI design.

Uploaded by

Chandra Shekar Medar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 10

VLSI Design

18EC72

Dept. of ECE
Module 3 Abhilash G.
Dept. of ECE Abhilash G.
Delay and Combinational Circuit Design

Abhilash G.
Assistant Professor,
Department of ECE,
Module-3
Delays & Combinational Circuit Design

• Delay: Introduction, Transient Response, RC


Delay Model, Linear Delay Model, Logical Efforts
of Paths (4.1 to 4.5 of TEXT2, except sub-
sections 4.3.7, 4.4.5, 4.4.6, 4.5.5 and 4.5.6).
• Combinational Circuit Design: Introduction,
Circuit families (9.1 to 9.2 of TEXT2, except
subsection 9.2.4).
TEXT1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo
Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill. 
TEXT2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E.
Weste, and David Money Harris, 4th Edition, Pearson Education.

Dept. of ECE Abhilash G. 2


Course Outcomes
After studying this course, students will be able to:
• Demonstrate understanding of MOS transistor theory, CMOS
fabrication flow and technology scaling.
• Draw the basic gates using the stick and layout diagrams with the
knowledge of physical design aspects.
• Demonstrate ability to design Combinational, sequential and
dynamic logic circuits as per the requirements
• Interpret Memory elements along with timing considerations
• Interpret testing and testability issues in VLSI Design

Dept. of ECE Abhilash G. 3


Combinational Circuit Design
Circuit Families – Static CMOS, Rationed Circuits, Cascode Voltage Switch Logic,
Pass Transistor Circuits

Dept. of ECE Abhilash G. 49


Static CMOS
Bubble Pushing, Compound gates, Input ordering delay effect, Asymmetric Gates, Skewed Gates

In CMOS technology to design and & or function, we use NAND and


NOR functions respectively,
In manual circuit design, this is often done through bubble pushing
Bubble Pushing CMOS stages are inherently inverting, so AND and
OR functions must be built from NAND and NOR gates. DeMorgan’s
law helps with this conversion:

Dept. of ECE Abhilash G. 50


Static CMOS
Bubble Pushing, Compound gates, Input ordering delay effect, Asymmetric Gates, Skewed Gates

Compouned gate – AOI, OAI

Dept. of ECE Abhilash G. 51


Static CMOS
Bubble Pushing, Compound gates, Input ordering delay effect, Asymmetric Gates, Skewed Gates

Skewed gates

Dept. of ECE Abhilash G. 52


Ratioed Circuits – use weak pull-up devices and strong pull-down devices. They reduce
the input capacitance and hence improve logical effort by eliminating large PMOS tran’ Loading the
inputs

Dept. of ECE Abhilash G. 53


CASCODE VOLTAGE SWITCH LOGIC(CVSL)

Dept. of ECE Abhilash G. 54


Pass Transistor

Dept. of ECE Abhilash G. 55

You might also like